Management of channel buffer in video decoders
DC
First Claim
1. A video decoding system comprising:
- means for buffering a video bitstream received from a transmission channel that includes picture data;
means, coupled to said buffering means, for reconstructing pictures from said picture data, said picture data being transferred from said buffering means to said means for reconstructing pictures when said buffering means receives all of said picture data for a single picture; and
means, coupled to said means for reconstructing pictures, for controlling the display of said reconstructed pictures, said display controlling means being synchronized with said picture reconstructing means.
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Abstract
A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer. In accordance with one aspect of the present invention, a display controller and picture reconstruction means are fabricated as an monolithic integrated circuit device.
147 Citations
21 Claims
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1. A video decoding system comprising:
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means for buffering a video bitstream received from a transmission channel that includes picture data; means, coupled to said buffering means, for reconstructing pictures from said picture data, said picture data being transferred from said buffering means to said means for reconstructing pictures when said buffering means receives all of said picture data for a single picture; and means, coupled to said means for reconstructing pictures, for controlling the display of said reconstructed pictures, said display controlling means being synchronized with said picture reconstructing means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 17)
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12. A video decoding system comprising:
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a channel buffer, coupled to a transmission channel for storing a video bitstream received from said transmission channel including picture data; a decoder coupled to said channel buffer; reconstructing means, coupled to said decoder, for reconstructing a picture from said picture data; picture storing means for storing said reconstructed picture; a display controller coupled to said picture storing means; and means for controlling said display controller in response to a state of said reconstructing means. - View Dependent Claims (13, 14, 15, 16)
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18. A process of decoding a video bitstream comprising the steps of:
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receiving a video bitstream including picture data; storing all the picture data for a single picture in a channel buffer; decoding said single picture data when said single picture data is stored by said channel buffer; reconstructing an image from said single picture data; and controlling the rate of a display controller in response to a rate of picture reconstruction, said display controller generating video output signals representative of said reconstructed picture. - View Dependent Claims (19, 20, 21)
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Specification
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- Resources
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Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
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Original AssigneeLSI Logic Corporation (Broadcom, Inc.)
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InventorsAuld, David R.
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Primary Examiner(s)Groody, James J.
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Assistant Examiner(s)Murrell, Jeffrey S.
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Application NumberUS08/143,198Time in Patent Office505 DaysField of Search348/426, 348/429, 348/714, 348/715, 348/716, 348/720US Class Current375/240.25CPC Class CodesH04N 19/152 by measuring the fullness o...H04N 19/423 characterised by memory arr...H04N 19/427 Display on the fly, e.g. si...H04N 19/50 using predictive coding H04...H04N 19/61 in combination with predict...H04N 21/4302 Content synchronisation pro...H04N 21/4382 Demodulation or channel dec...H04N 21/44004 involving video buffer mana...
