Circuits, systems and methods for improving page accesses and block transfers in a memory system
DC CAFC
First Claim
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1. A memory comprising:
- an array of rows and columns of volatile memory cells;
addressing circuitry for providing access to selected ones of said memory cells;
master read/write circuitry for reading and writing data into said selected ones of said cells;
first slave circuitry for storing data for exchange with said master read/write circuitry;
second slave circuitry for storing data for exchange with said master read/write circuitry; and
control circuitry for controlling exchange of data between said master read/write circuitry and said first and second slave circuitry, said control circuitry operable during a move operation to;
control sensing by said master read/write circuitry of data from a said row in said array selected by said addressing circuitry;
control transfer of said data from said master read/write circuitry to a selected one of said first and second slave circuitry; and
control writing of said data through said master read/write circuitry to a second said row in said array selected by said addressing circuitry.
8 Assignments
Litigations
1 Petition
Reexamination
Accused Products
Abstract
A memory 200 is provided which includes an array 201 of volatile memory cells 202. Addressing circuitry 205, 213 is included for providing access to selected ones of the memory cells 202. Master read/write circuitry 208 is included for reading and writing data into the selected memory cells 202. First slave circuitry 210, 211 is provided for storing data for exchange with the master read/write circuitry 208. Second slave circuitry 210/211 is also provided for storing data for exchange with the master read/write circuitry 208. Control circuitry 206, 214, 215 controls the exchanges of data between the master read/write circuitry 208 and the first and second slave circuitry 210, 211.
8 Citations
19 Claims
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1. A memory comprising:
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an array of rows and columns of volatile memory cells; addressing circuitry for providing access to selected ones of said memory cells; master read/write circuitry for reading and writing data into said selected ones of said cells; first slave circuitry for storing data for exchange with said master read/write circuitry; second slave circuitry for storing data for exchange with said master read/write circuitry; and control circuitry for controlling exchange of data between said master read/write circuitry and said first and second slave circuitry, said control circuitry operable during a move operation to; control sensing by said master read/write circuitry of data from a said row in said array selected by said addressing circuitry; control transfer of said data from said master read/write circuitry to a selected one of said first and second slave circuitry; and control writing of said data through said master read/write circuitry to a second said row in said array selected by said addressing circuitry. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory system comprising:
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an array of memory cells arranged in rows and columns, each said row associated with a conductive wordline and each said column associated with a conductive bitline; a row decoder coupled to said wordlines; a bank of master sense amplifiers coupled to said bitlines; a plurality of banks of slave sense amplifiers coupled to said master sense amplifiers; a column decoder coupled to each of the plurality of banks of slave sense amplifiers; and control circuitry coupled to said row decoder, said bank of master sense amplifiers and said banks of slave sense amplifiers, said control circuitry including mode control circuitry coupled to said row decoder and said master sense amplifiers and multiplexer control circuitry coupled to said mode control circuitry and said plurality of banks of slave sense amplifiers, said control circuitry operable during a move operation to; control sensing by said master sense amplifiers of data from a said row in said array selected by said row decoder; control transfer of said data from said master sense amplifiers to a selected one of said banks of slave sense amplifiers; control writing of said data through said master sense amplifiers to a second said row in said array selected said row decoder. - View Dependent Claims (8, 9, 10, 11)
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12. A memory system comprising:
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an array of memory cells arranged in rows and columns, each said row associated with a conductive wordline and each said column associated with a conductive bitline; a row decoder coupled to said wordlines; a bank of master sense amplifiers coupled to said bitlines; a plurality of banks of slave sense amplifiers coupled to said master sense amplifiers; a column decoder coupled to each of the plurality of banks of slave sense amplifiers; and said control circuitry including mode control circuitry coupled to said row decoder and said master sense amplifiers and multiplexer control circuitry coupled to said mode control circuitry and said first and second banks of slave sense amplifiers, said control circuitry operable during a block move operation to; control sensing by said master sense amplifiers of data from a said row in said array selected by said row decoder; control transfer of said data from said master sense amplifiers to a selected one of said banks of slave sense amplifiers; control shifting of said data from a first set of slave sense amplifiers to a second set of slave sense amplifiers within said selected bank of slave amplifiers; and control writing of said data through said master sense amplifiers to ones of said cells along said selected said row associated with said bitlines coupled to said second set of slave sense amplifiers.
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13. A memory comprising:
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an array of dynamic random access memory cells arranged in rows and columns, each said row including a conductive wordline and each said column including a conductive bitline; row decoder circuitry coupled to said wordlines for selecting a said row in response to a row address; master sense amplifier circuitry coupled to said bitlines for reading and writing data to ones of said cells along a selected said row; column decoder circuitry coupled to a data bus; first latching circuitry coupled to said sense amplifier circuitry by a first local bus and to said column decoder by a second local bus for latching data being exchanged between said sense amplifier circuitry and said column decoder; second latching circuitry coupled to said sense amplifier circuitry by said first local bus and to said column decoder by said second local bus for latching data being exchanged between said sense amplifier circuitry and said column decoder; and control circuitry for; causing said master sense amplifier circuitry to sense data from a said row selected by said row decoder; transferring said data from said master sense amplifier circuitry to said first slave sense amplifier circuitry; writing said data from said first slave sense amplifiers to said second row selected by said row decoder; causing said master sense amplifier circuitry to sense data from a third said row selected by said row decoder; transferring said data from said master sense amplifier circuitry to said second slave sense amplifier circuitry; and writing said data from said second slave sense amplifiers to a fourth said row selected by said row decoder. - View Dependent Claims (14, 15, 16)
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17. A method of performing a block transfer within a memory including an array of memory cells arranged in rows and columns, each said row associated with a conductive wordline and each said column associated with a conductive bitline, comprising the steps of:
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selecting a row in the array; sensing the bitlines of the array to read data stored in the cells of the selected row with a bank of master sense amplifiers; latching the data read from the cells of the selected row in a bank of slave sense amplifiers; writing the data stored in the slave sense amplifiers through the master sense amplifiers to different cells in the array. - View Dependent Claims (18, 19)
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Specification
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Litigation Data
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Current AssigneeIntellectual Ventures II LLC (Intellectual Ventures LLC)
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Original AssigneeCirrus Logic Incorporated
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InventorsRunas, Michael E.
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Primary Examiner(s)ZARABIAN, AMIR
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Application NumberUS08/315,934Time in Patent Office536 DaysField of Search365/205, 365/189.05, 365/208, 365/238.5, 365/189.04, 365/189.12, 365/207US Class Current365/189.05CPC Class CodesG11C 7/1021 Page serial bit line access...G11C 7/1039 using pipelining techniques...
