High performance, low cost microprocessor
DC CAFC
First Claim
1. A microprocessor, which comprises a main central processing unit and a separate direct memory access central processing unit in a single integrated circuit comprising said microprocessor, said main central processing unit having an arithmetic logic unit, a first push down stack with a top item register and a next item register, connected to provide inputs to said arithmetic logic unit, an output of said arithmetic logic unit being connected to said top item register, said top item register also being connected to provide inputs to an internal data bus, said internal data bus being bidirectionally connected to a loop counter, said loop counter being connected to a decrementer, said internal data bus being bidirectionally connected to a stack pointer, return stack pointer, mode register and instruction register, said internal data bus being connected to a memory controller, to a Y register of a return push down stack, an X register and a program counter, said Y register, X register and program counter providing outputs to an internal address bus, said internal address bus providing inputs to said memory controller and to an incrementer, said incrementer being connected to said internal data bus, said direct memory access central processing unit providing inputs to said memory controller, said memory controller having an address/data bus and a plurality of control lines for connection to a random access memory.
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Reexamination
Accused Products
Abstract
A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down stack (74), which has a top item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register (76) by line (86). The output of the top item register at (82) is also connected by line (88) to an internal data bus (90). A loop counter (92) is connected to a decrementer (94) by lines (96) and (98). The loop counter (92) is bidirectionally connected to the internal data bus (90) by line (100). Stack pointer (102), return stack pointer ( 104), mode register (106) and instruction register (108) are also connected to the internal data bus (90) by lines (110), (112), (114) and (116), respectively. The internal data bus (90) is connected to memory controller (118) and to gate (120). The gate (120) provides inputs on lines (122), (124), and (126) to X register (128), program counter (130) and Y register (132) of return push down stack (134). The X register (128), program counter (130) and Y register (132) provide outputs to internal address bus (136) on lines (138), (140) and (142). The internal address bus provides inputs to the memory controller (118) and to an incrementer (144). The incrementer (144) provides inputs to the X register, program counter and Y register via lines (146), (122), (124) and (126). The DMA CPU (72) provides inputs to the memory controller (118) on line (148). The memory controller (118) is connected to a RAM by address/data bus (150) and control lines (152).
57 Citations
10 Claims
- 1. A microprocessor, which comprises a main central processing unit and a separate direct memory access central processing unit in a single integrated circuit comprising said microprocessor, said main central processing unit having an arithmetic logic unit, a first push down stack with a top item register and a next item register, connected to provide inputs to said arithmetic logic unit, an output of said arithmetic logic unit being connected to said top item register, said top item register also being connected to provide inputs to an internal data bus, said internal data bus being bidirectionally connected to a loop counter, said loop counter being connected to a decrementer, said internal data bus being bidirectionally connected to a stack pointer, return stack pointer, mode register and instruction register, said internal data bus being connected to a memory controller, to a Y register of a return push down stack, an X register and a program counter, said Y register, X register and program counter providing outputs to an internal address bus, said internal address bus providing inputs to said memory controller and to an incrementer, said incrementer being connected to said internal data bus, said direct memory access central processing unit providing inputs to said memory controller, said memory controller having an address/data bus and a plurality of control lines for connection to a random access memory.
Specification
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- Resources
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Current AssigneeCharles H. Moore, Patriot Scientific Corporation, Technology Properties Limited LLC
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Original AssigneeNanotronics (Patriot Scientific Corporation)
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InventorsMoore, Charles H., Fish, Russell H. III
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Primary Examiner(s)Eng, David Y.
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Application NumberUS08/480,206Time in Patent Office384 DaysField of Search395/375, 395/500, 395/775, 395/800US Class Current712/32CPC Class CodesG06F 12/0875 with dedicated cache, e.g. ...G06F 15/7832 on one IC chip (single chip...G06F 2207/581 Generating an LFSR sequence...G06F 2207/583 Serial finite field impleme...G06F 7/5272 with row wise addition of p...G06F 7/584 using finite field arithmet...G06F 7/785 having a sequence of storag...G06F 9/30 Arrangements for executing ...G06F 9/30036 Instructions to perform ope...G06F 9/30054 Unconditional branch instru...G06F 9/30065 Loop control instructions; ...G06F 9/30069 Instruction skipping instru...G06F 9/30145 Instruction analysis, e.g. ...G06F 9/30167 of immediate specifier, e.g...G06F 9/325 for loops, e.g. loop detect...G06F 9/3802 Instruction prefetchingG06F 9/3806 using address prediction, e...G06F 9/381 Loop bufferingG06F 9/3824 Operand accessingG06F 9/3867 using instruction pipelines
