Memory architecture and devices, systems and methods utilizing the same

US 5,568,431 A
Filed: 09/21/1995
Issued: 10/22/1996
Est. Priority Date: 09/12/1994
Status: Expired due to Term

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1. A memory device comprising:

a plurality of arrays of memory cells;

a plurality of registers, each of said registers for exchanging parallel bits of data with a corresponding one of said arrays; and

data transfer circuitry for transferring parallel bits of data from any selected one of said arrays through the corresponding said register to any other selected one of said arrays through the corresponding said register.

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Abstract

A memory 200 is provided including a plurality of arrays 202 of memory cells 203. A plurality of registers 211 are also provided, each register 211 for exchanging parallel bits of data with a corresponding one of the arrays 202. Data transfer circuitry 210, 213 is included for transferring parallel bits of data from any selected one of the arrays 202 through the corresponding register 211 to any other selected one of the arrays 202 through the corresponding register 211.

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20 Claims

1. A memory device comprising:
- a plurality of arrays of memory cells;
  
  a plurality of registers, each of said registers for exchanging parallel bits of data with a corresponding one of said arrays; and
  
  data transfer circuitry for transferring parallel bits of data from any selected one of said arrays through the corresponding said register to any other selected one of said arrays through the corresponding said register.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- - 2. The memory device of claim 1 wherein said data transfer circuitry comprises:
    - addressing circuitry for reading data from selected ones of said cells of a source said array and for writing data to selected ones of said cells of a destination said array;
      
      a bus coupled to said each of said registers for transferring data between said source array and said destination array; and
      
      input/output control circuitry for selectively controlling the exchange of data between said registers associated with said source and destination arrays and said bus.
  - 3. The memory device of claim 2 wherein said addressing circuitry comprises first row and column decoders associated with said source array and second row and column decoders associated with said destination array.
  - 4. The memory device of claim 1 wherein said addressing circuitry includes circuitry for generating a sequence of addresses for transferring a block of data from said source array to said destination array.
  - 5. The memory of claim 4 wherein said circuitry for generating generates a sequence of addresses for transferring a block of data in response to a received start address.
  - 6. The memory device of claim 1 wherein each said register comprises a shift register.
  - 7. The memory device of claim 6 wherein each said shift register includes a plurality of taps.
  - 8. The memory device of claim 7 wherein each said array is associated with a plurality of shift registers each offset by a selected number of bit positions.

9. A memory subsystem comprising:
- a plurality of arrays of memory cells each arranged in rows and columns;
  
  for each said array, a row decoder and a column decoder for accessing selected ones of said cells of said array;
  
  for each said array, an associated register having a first parallel port coupled to said column decoder;
  
  a common bus coupled to a second parallel port of each said register; and
  
  circuitry for coupling data from accessed ones of said cells of a first selected one of said arrays to accessed ones of said cells of a second selected one of said arrays via said parallel ports of said associated registers and said bus.
- View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
- - 10. The memory subsystem of claim 9 wherein each said row decoder includes row address increment circuitry for accessing a block of data from a plurality of rows in the corresponding said array.
  - 11. The memory subsystem of claim 9 wherein a selected said register has a bit-length which is greater than the number of columns of the corresponding said array.
  - 12. The memory subsystem of claim 9 and further comprising a plurality of offset shift registers associated with each said array, said plurality of registers loaded substantially simultaneously with loading said register associated with the corresponding said array.
  - 13. The memory subsystem of claim 9 wherein each said register comprises a shift register.
  - 14. The memory subsystem of claim 9 wherein said memory subsystem is fabricated on a single chip.
  - 15. The memory subsystem of claim 9 wherein said memory cells comprise dynamic random access memory cells.
  - 16. The memory subsystem of claim 9 wherein said memory cells comprise static random access memory cells.

17. A method of transferring data in a memory including a plurality of arrays of memory cells, addressing circuitry for accessing selected ones of said cells of a selected array, a common bus, and a plurality of registers each for controlling the exchange of data between a corresponding array and the common bus, the method comprising the steps of:
- presenting at least one source address to the addressing circuitry to read data from selected cells of a selected source array;
  
  transferring the data from the source array to the common bus via the corresponding register;
  
  transferring the data to the register corresponding to a destination array; and
  
  presenting at least one destination address to the addressing circuitry to write data into selected cells of the destination array.
- View Dependent Claims (18, 19, 20)
- - 18. The method of claim 17 and further comprising the steps of:
    - modifying the source address within the addressing circuitry to read second data from second selected cells of the source array;
      
      modifying the destination address within the addressing circuitry to write second data to second selected cells of the destination array; and
      
      transferring the second data from the source array to the destination array via the bus and the registers corresponding to the source and destination array.
  - 19. The method of claim 18 wherein said steps of modifying comprise the substep of incrementing a row address.
  - 20. The method of claim 18 wherein said steps of modifying comprises the substep of modifying a column address.

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Current Assignee
Intellectual Ventures II LLC (Intellectual Ventures LLC)
Original Assignee
Cirrus Logic Incorporated
Inventors
Rao, G. R. Mohan
Primary Examiner(s)
Nelms, David C.
Assistant Examiner(s)
LE, VU ANH

Application Number

US08/531,755
Time in Patent Office

397 Days
Field of Search

365/189.12, 365/230.05, 365/230.09, 365/230.03, 365/231, 365/239, 365/240
US Class Current

365/189.12
CPC Class Codes

G11C 7/1036 using data shift registers

Memory architecture and devices, systems and methods utilizing the same

First Claim

7 Assignments

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Abstract

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20 Claims

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Memory architecture and devices, systems and methods utilizing the same

First Claim

7 Assignments

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Abstract

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20 Claims

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