VGA controller circuitry
DC
First Claim
Patent Images
1. A monolithic integrated circuit comprising:
- programmable clock circuit means for producing a video memory clock signal and a video dot clock signal;
a video controller coupled to said programmable clock circuit means for receiving the video memory clock signal and the video dot clock signal and for producing a video information data stream;
random-access memory means, coupled to said video controller, for receiving the video information data stream and producing a video display information data stream; and
digital-to-analog converter means, coupled to both said random-access memory and to said video controller, for selectively receiving either the video information data stream or the video display information data stream as received data and for converting the received data to analog video signals.
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Accused Products
Abstract
The "chip set" of a graphics adapter interface card is reduced to a monolithic integrated circuit that includes a programmable analog clock circuit for producing a video memory clock and a video dot clock. A digital graphics adapter controller is responsive to the video memory clock and the video dot clock to produce a video information stream. A random-access memory is responsive to the video information stream to produce a video display information stream, and a digital-to-analog converter is responsive to the video display information stream to convert the video display information stream to analog signals for application to a video display device.
22 Citations
11 Claims
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1. A monolithic integrated circuit comprising:
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programmable clock circuit means for producing a video memory clock signal and a video dot clock signal; a video controller coupled to said programmable clock circuit means for receiving the video memory clock signal and the video dot clock signal and for producing a video information data stream; random-access memory means, coupled to said video controller, for receiving the video information data stream and producing a video display information data stream; and digital-to-analog converter means, coupled to both said random-access memory and to said video controller, for selectively receiving either the video information data stream or the video display information data stream as received data and for converting the received data to analog video signals. - View Dependent Claims (2, 3, 4)
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5. An arrangement comprising:
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a monolithic integrated circuit having; programmable clock circuit means for receiving a reference clock signal and devisor data and for dividing said reference clock signal by said devisor data to produce a video memory clock signal and a video dot clock signal; a video controller coupled to said programmable clock circuit for providing said programmable clock circuit means with said devisor data and for receiving the video memory clock signal and the video dot clock signal and for producing a video information data stream; random-access memory means, coupled to said video controller, for receiving the video information data stream and producing a video display information data stream; digital-to-analog converter means, coupled to said random-access memory means, for receiving the video information data stream and converting the video information data stream to analog video signals; and programmable memory means coupled to the monolithic integrated circuit for storing said devisor data to be received by the programmable clock circuit means. - View Dependent Claims (6, 7, 8)
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9. A monolithic integrated circuit comprising:
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a programmable clock circuit responsive to a reference clock signal and devisor data and generating a video memory clock signal and a video dot clock signal; a video controller receiving the video memory clock signal and the video dot clock signal and producing a video information data stream from data received from a video RAM; a random-access memory producing a video display information data stream in response to the video information data stream from said video controller; a digital-to-analog converter converting received digital data to analog video signals; and a selector supplying one of said video information data stream from the video controller and said video display information data stream from said random-access memory to said digital-to-analog converter as said received digital data. - View Dependent Claims (10, 11)
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Specification
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Litigation Data
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Current AssigneeS3 Graphics Co., Ltd. (HTC Corporation)
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Original AssigneeCirrus Logic Incorporated
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InventorsChang, Chieh, Lee, Man S., Lushtak, Alex
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Primary Examiner(s)Weldon, Ulysses
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Assistant Examiner(s)Mengistu, Amare
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Application NumberUS08/147,456Time in Patent Office1,124 DaysField of Search345/132, 345/190, 345/201, 345/185, 395/325, 395/400, 395/164, 395/425, 357/45, 357/201, 257/203, 328/63, 328/104US Class Current345/519CPC Class CodesG09G 5/18 Timing circuits for raster ...G09G 5/363 Graphics controllers
