Continuous page random access memory and systems and methods using the same

US 5,581,513 A
Filed: 04/19/1995
Issued: 12/03/1996
Est. Priority Date: 04/19/1995
Status: Expired due to Term

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1. A random access memory comprising:

input/output circuitry;

an array of random access memory cells arranged in rows and columns;

row control circuitry for selecting in response to a row address a said row of cells for access;

column control circuitry for controlling access to locations along said selected row, each said location comprising at least one said memory cell, said column control circuitry operable to;

sequentially access a first plurality of said locations along said selected row through said input/output circuitry; and

simultaneously access a second plurality of said locations along said selected row; and

auxiliary memory circuitry for interfacing exchanges of data between said second plurality of locations and said input/output circuitry, said auxiliary memory circuitry exchanging data words with corresponding ones of said second plurality of locations of said array in parallel and with said input/output circuitry in serial.

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Abstract

A random access memory 200 is provided which includes input/output circuitry 205 and an array 202 of random access memory cells 201 arranged in rows and columns. Row decoder circuitry 206 is provided for selecting in response to a row address a row of cells in array 202 for access. Column control circuitry 207, 208 is included for controlling access to locations along the selected row, each location comprising at least one memory cell 201. The column control circuitry 207, 208 is operable to sequentially access a first plurality of locations along the selected row through input/output circuitry 205 and simultaneously access a second plurality of locations along the selected row. Auxiliary memory circuitry 209 is included for interfacing exchanges of data between the second plurality of locations and input/output circuitry 205, auxiliary memory circuitry 209 exchanging words with corresponding ones of the second plurality of locations in array 202 in parallel and with input/output circuitry 205 in serial.

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21 Claims

1. A random access memory comprising:
- input/output circuitry;
  
  an array of random access memory cells arranged in rows and columns;
  
  row control circuitry for selecting in response to a row address a said row of cells for access;
  
  column control circuitry for controlling access to locations along said selected row, each said location comprising at least one said memory cell, said column control circuitry operable to;
  
  sequentially access a first plurality of said locations along said selected row through said input/output circuitry; and
  
  simultaneously access a second plurality of said locations along said selected row; and
  
  auxiliary memory circuitry for interfacing exchanges of data between said second plurality of locations and said input/output circuitry, said auxiliary memory circuitry exchanging data words with corresponding ones of said second plurality of locations of said array in parallel and with said input/output circuitry in serial.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- - 2. The memory of claim 1 wherein said auxiliary memory circuitry is operable to exchange data between said input/output circuitry and said auxiliary memory circuitry during an interval when said row control circuitry is preparing to select a new row in said array.
  - 3. The memory of claim 1 wherein said first plurality of locations are sequentially accessed prior to simultaneous access of said second plurality of locations during a read form said array.
  - 4. The memory of claim 1 wherein said second plurality of locations are simultaneously accessed prior to sequential access of said first plurality of locations during a write from said array.
  - 5. The memory of claim 1 wherein said row control circuitry includes:
    - row address input circuitry for receiving and latching-in said row address in response to a row address strobe; and
      
      a row decoder for activating a wordline associated with said selected row in said array corresponding to said received address.
  - 6. The memory of claim 1 wherein said column control circuitry includes:
    - a column decoder/sense amplifier circuitry for activating bitlines associated with each cell of each said location along said selected row;
      
      page mode circuitry for causing said column decoder/sense amplifier circuitry to sequentially activate said bitlines associated with said cells of said first plurality of locations to thereby provide sequential access to said first plurality of locations;
      
      trigger circuitry for causing said column decoder to simultaneously activate said bitlines associated with said cells of said second plurality of locations.
  - 7. The memory of claim 6 wherein said page mode circuitry includes address incrementation circuitry for generating a sequence of addresses corresponding for sequentially activating said bitlines.
  - 8. The memory of claim 1 wherein said memory cells comprise dynamic random access memory cells.

9. A continuous page memory comprising:
- input/output circuitry;
  
  an array of rows and columns of random access memory cells;
  
  row access control circuitry operable during a row access cycle of a predetermined time interval to latch-in a received row address with a row address strobe and select a corresponding said row in said array in response;
  
  an auxiliary memory for exchanging a sequence of data words with said input/output circuitry during said row access cycle, a number of said sequence of data words selected as a function of said time interval; and
  
  location access control circuitry for providing access to storage locations along said selected row, each said storage location comprising at least one said memory cell, said location access control circuitry operable during a data access cycle following said row access cycle to;
  
  during a first selected time period of said data access cycle allow for page accesses between a first plurality of said locations along said selected row and said input/output circuitry; and
  
  during a second selected time period of said data access cycle allow for the simultaneous exchange of words of data between said auxiliary memory and corresponding ones of a second plurality of locations along said selected row.
- View Dependent Claims (10, 11, 12, 13, 14, 15)
- - 10. The memory of claim 9 wherein said first selected time interval precedes said second time interval during a read from said array.
  - 11. The memory of claim 10 wherein said location access control circuitry is operable during said read to:
    - latch-in an initial column address corresponding to an initial one of said first plurality of locations in response to a column address strobe;
      
      increment from said initial column address to generate a plurality of column addresses to subsequent ones of said first plurality of locations; and
      
      address said second plurality of locations simultaneously after said last location of said first plurality of locations has been read.
  - 12. The memory of claim 9 wherein said second selected time interval precedes said first selected time interval during a write to said array.
  - 13. The memory of claim 12 wherein said location access control circuitry is operable during said write to:
    - latch-in a column address to at least one of said second plurality of locations and in response allow said write to said second plurality of locations with data from said auxiliary memory; and
      
      increment from a first column address corresponding to a first one of said first plurality of locations to generate addresses to allow sequential access to subsequent ones of said first plurality of locations.
  - 14. The memory of claim 9 wherein said location access control circuitry comprises:
    - a column decoder/sense amplifier circuitry for activating bitlines associated with each cell of each said location along said selected row;
      
      page mode circuitry for causing said column decoder/sense amplifier circuitry to sequentially activate said bitlines associated with said cells of said plurality of first plurality of locations to thereby provide sequential access to said first plurality of locations;
      
      trigger circuitry for causing said column decoder to simultaneously activate said bitlines associated with said cells of said second plurality of locations.
  - 15. The memory of claim 9 wherein said first plurality of locations and said second plurality of locations are adjacently disposed on said selected row.

16. A continuous page random access memory comprising:
- an array of rows and columns of random access memory cells;
  
  row access control circuitry operable during a each of a plurality of row access cycles of a predetermined time interval to latch-in a received row address with a row address strobe and select a corresponding said row in said array in response;
  
  an auxiliary memory; and
  
  read/write control circuitry for reading and writing data into selected locations in said array during each of a plurality of data access cycles occurring between said row access cycles, each said location comprising at least one said memory cell, said read/write control circuitry operable to;
  
  during a first selected time period of each said data access cycle allow for page accesses to a first plurality of said locations along said selected row through said input/output circuitry; and
  
  during a second selected time period of each said data access cycle allow for a parallel exchange of words of data between said auxiliary memory and corresponding ones of a second plurality of locations along said selected row.
- View Dependent Claims (17, 18, 19)
- - 17. The memory of claim 16 wherein said first selected time period precedes said second selected time period in said active cycle during a read operation.
  - 18. The memory of claim 16 wherein said second selected time period precedes said second selected time period in said active period during a write operation.
  - 19. The memory of claim 16 wherein said auxiliary memory control circuitry implements a serial exchange of data between said auxiliary memory and said input/output circuitry to maintain a continuous page access during each said row access cycle.

20. A method of performing continuous page accesses in a memory system having an array of rows and columns of memory cells, storage locations comprising at least one of the memory cells on a given row accessible during a data access cycle and row selecting occurring during a row access cycle, the method comprising the steps of:
- during a first selected time period of each data access cycle accessing a first plurality of the locations along a selected one of the rows through a memory system input/output;
  
  during a second selected time period of each data access cycle exchanging words of data in parallel between an auxiliary memory and corresponding ones of a second plurality of the storage locations along the selected row; and
  
  during each row access cycle, exchanging data between the memory input/output and the auxiliary memory.
- View Dependent Claims (21)
- - 21. The method of claim 20 wherein said step of exchanging data between the memory input/output and the auxiliary memory comprises the step of exchanging serial words of data.

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Current Assignee
Intellectual Ventures II LLC (Intellectual Ventures LLC)
Original Assignee
Cirrus Logic Incorporated
Inventors
Mohan Rao, G. R.
Primary Examiner(s)
NGUYEN, TAN

Application Number

US08/423,825
Time in Patent Office

594 Days
Field of Search

365/238.5, 365/235, 365/189.01, 365/49, 365/219, 365/220
US Class Current

365/238.5
CPC Class Codes

G11C 7/1021 Page serial bit line access...

G11C 7/103 using serially addressed re...

Continuous page random access memory and systems and methods using the same

First Claim

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Abstract

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21 Claims

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Continuous page random access memory and systems and methods using the same

First Claim

6 Assignments

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Abstract

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21 Claims

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