High-order delta sigma analog-to-digital converter with unit-delay integrators
DC
First Claim
Patent Images
1. An oversampled interpolative modulator for receiving an input analog signal and generating an output digital signal, said modulator comprising:
- a plurality of cascaded unit-delay integrators comprising at least first and second unit-delay integrators and at least first and second differential summing junctions, the input of said first summing junction coupled to receive an input analog signal and the output of said first summing junction coupled to the input of said first integrator, the input of said second summing junction coupled to the output of said first integrator and the output of said second summing junction coupled to the input of said second unit-delay integrator;
a multi-bit analog-to-digital converter coupled to the output of the cascaded plurality of unit-delay integrators; and
a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the output of said digital-to-analog converter being coupled to the inputs of each of said differential summing junctions.
1 Assignment
Litigations
0 Petitions
Accused Products
Abstract
A delta sigma modulator which enables each cascaded integrator to settle independently within a full clock period and uses binomial coefficients in the feedback paths to obtain the required sinusoidal shaping of quantizer error, achieves an increase in both the sampling rate and the order to improve resolution. Using a multi-bit quantizer also improves modulator resolution. In one embodiment, the modulator includes a plurality of cascaded unit-delay integrators and utilizes binomial coefficient scaling in the feedback loop. A multi-bit analog-to-digital converter is coupled to receive the output signal of the cascaded unit-delay integrators. The feedback loop includes a multi-bit digital-to-analog converter coupled to the output of the multi-bit analog-to-digital converter. The output of the digital-to-analog converter is coupled to the inputs of at least the first and second differential summing junctions.
23 Citations
10 Claims
-
1. An oversampled interpolative modulator for receiving an input analog signal and generating an output digital signal, said modulator comprising:
-
a plurality of cascaded unit-delay integrators comprising at least first and second unit-delay integrators and at least first and second differential summing junctions, the input of said first summing junction coupled to receive an input analog signal and the output of said first summing junction coupled to the input of said first integrator, the input of said second summing junction coupled to the output of said first integrator and the output of said second summing junction coupled to the input of said second unit-delay integrator; a multi-bit analog-to-digital converter coupled to the output of the cascaded plurality of unit-delay integrators; and a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the output of said digital-to-analog converter being coupled to the inputs of each of said differential summing junctions. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A delta sigma analog-to-digital converter comprising:
an oversampled interpolative modulator for receiving an input analog signal to be converted and generating an output digital signal; a digital filter coupled to receive the output digital signal of said oversampled interpolative modulator for generating a filtered digital output signal; and a decimator coupled to receive the filtered digital output signal of said digital filter for decreasing the sampling rate of said filtered digital output signal; said oversampled interpolative modulator comprising; a plurality of cascaded unit-delay integrators comprising at least first and second unit-delay integrators and at least first and second differential summing junctions, the input of said first summing junction coupled to receive an input analog signal and the output of said first summing junction coupled to the input of said first integrator, the input of said second summing junction coupled to the output of said first integrator and the output of said second summing junction coupled to the input of said second unit-delay integrator; a multi-bit analog-to-digital converter coupled to the output of the cascaded plurality of unit-delay integrators; and a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the output of said digital-to-analog converter being coupled to the inputs of each of said differential summing junctions. - View Dependent Claims (7, 8, 9, 10)
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
Litigation Data
-
Current AssigneeGeneral Electric Company
-
Original AssigneeGeneral Electric Company
-
InventorsRibner, David Byrd, Hoe, David Henry Kenneth
-
Primary Examiner(s)Young, Brian K.
-
Application NumberUS08/650,282Time in Patent Office526 DaysField of Search341/143, 341/76, 341/77, 375/27, 375/29, 375/33US Class Current341/143CPC Class CodesH03M 3/374 Relaxation of settling time...H03M 3/388 by storing corrected or cor...H03M 3/424 the quantiser being a multi...H03M 3/454 with distributed feedback, ...
