Multiple-bank memory architecture and systems and methods using the same

US 5,687,132 A
Filed: 10/26/1995
Issued: 11/11/1997
Est. Priority Date: 10/26/1995
Status: Expired due to Term

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1. A memory comprising:

a first plurality of columns of memory cells each including at least one conductive bitline;

a second plurality of columns of memory cells each including at least one conductive bitline; and

a plurality of gates organized in independently controlled groups for selectively coupling said bitlines of a selected group of said first plurality of columns with a group of said bitlines of said second plurality of columns for transferring a at least one bit of data from a selected cell of said first plurality of columns of cells to a selected cell of said second plurality of columns of cells.

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Abstract

A memory 20 is disclosed including a first column of memory cells including a conductive bitline 202 and a second column of memory cells also including a conductive bitline 202. A gate 203 is provided for selectively coupling the bitline 202 of the first column with the bitline 202 of the second column for transferring a bit of data from a selected cell of the first column to a selected cell of the second column.

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30 Claims

1. A memory comprising:
- a first plurality of columns of memory cells each including at least one conductive bitline;
  
  a second plurality of columns of memory cells each including at least one conductive bitline; and
  
  a plurality of gates organized in independently controlled groups for selectively coupling said bitlines of a selected group of said first plurality of columns with a group of said bitlines of said second plurality of columns for transferring a at least one bit of data from a selected cell of said first plurality of columns of cells to a selected cell of said second plurality of columns of cells.
- View Dependent Claims (2, 3, 4, 5, 14, 15)
- - 2. The memory of claim 1 wherein each said gate comprises a field effect transistor.
  - 3. The memory of claim 1 wherein said memory cells comprises dynamic random access memory cells.
  - 4. The memory of claim 1 wherein said first column of cells comprises one of a plurality of columns of memory cells forming a first subarray and said second column of cells comprises one of a plurality of columns of cells forming a second subarray.
  - 5. The memory of claim 4 wherein said first and second subarrays each comprise a plurality of rows of cells, each said row including a conductive wordline, a wordline of a said row of said first subarray controlled by a first row decoder and a wordline of a said row of said second subarray controlled by a second row decoder.
  - 14. The memory of claim 1 wherein said first and second column decoders respond to different address sets respectively.
  - 15. The memory of claim 14 and further comprising a first first-in-first-out memory coupled to said first column decoder and a second first-in-first-out memory coupled to said second column decoder.

6. A memory subsystem comprising:
- a first subarray of memory cells arranged in rows and columns, each said column associated with a conductive bitline and each said row associated with a conductive wordline;
  
  a second subarray of memory cells arranged in rows and columns, each said column associated with a conductive bitline and each said row associated with a conductive wordline;
  
  circuitry for independently coupling selected groups of said bitlines of said first subarray with corresponding groups of said bitlines of said second subarray;
  
  a first column decoder coupled to said bitlines of said first subarray for randomly accessing selected cells along a selected row in said first subarray; and
  
  a second column decoder coupled to said bitlines of said second subarray for randomly accessing selected cells along a selected row in said second subarray.
- View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
- - 7. The memory subsystem of claim 6 and further comprising column control circuitry operable to cause said circuitry for gating to coupled selected ones of said bitlines in response to a received control signal.
  - 8. The memory of claim 6 wherein said bitlines of each of said first and second subarrays comprise folded bitlines.
  - 9. The memory of claim 6 wherein said circuitry for coupling comprises a plurality of gates.
  - 10. The memory of claim 9 wherein said plurality of gates comprises a plurality of field effect transistors.
  - 11. The memory of claim 8 and further comprising control circuitry for causing said circuitry for coupling to couple a said bitline and a complementary said bitline of said first subarray with a said bitline and a complementary said bitline of said second subarray in response to a received control signal.
  - 12. The memory of claim 6 and further comprising a first row decoder coupled to said wordlines of said first subarray and a second row decoder coupled to said wordlines of said second subarray.
  - 13. The memory of claim 12 wherein said first and second row decoders respond to different address sets respectively.

16. A memory device comprising:
- a first subarray of rows and columns of dynamic random access memory cells, each said column including a bitline and each said row including a wordline;
  
  a second subarray of rows and columns of dynamic random access memory cells, each said column including a bitline and each said row including a wordline;
  
  a first row decoder for selecting a said wordline in said first subarray in response to a first set of row addresses;
  
  a second row decoder for selecting a said wordline in said second subarray in response to a second set of row addresses;
  
  a first column decoder for selecting at least one bitline in said first subarray for random access in response to a first set of column addresses;
  
  a second column decoder for selecting at least one bitline in said second subarray for random access in response to a second set of column addresses;
  
  a first plurality of gates for selectively coupling at least one bitline of a corresponding group of bitlines in said first subarray with at least one bitline of a corresponding group of bitlines in said second subarray, said first plurality of gates controlled by a first control signal; and
  
  a second plurality of gates for selectively coupling at least one bitline in a corresponding group of bitlines in said first subarray with at least one bitline of a corresponding group of bitlines in said second subarray.
- View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
- - 17. The memory device of claim 16 wherein first set of row addresses is equivalent to said second set of row addresses.
  - 18. The memory device of claim 16 wherein said first set of column addresses is equivalent to said second set of column addresses.
  - 19. The memory device of claim 16 wherein said bitlines of said first and second subarrays comprise folded bitlines arranged in pairs of complementary bitlines, a sense amplifier shared by said complementary bitlines of a selected said pair.
  - 20. The memory device of claim 16 and further comprising latching circuitry associated with said first subarray for temporarily latching data read from at least one cell in said first subarray during a transfer through at least one of said gates to a cell in said second subarray.
  - 21. The memory device of claim 16 wherein said plurality of gates comprises a plurality of field effect transistors each having a current path coupling a said bitline in said first subarray with a said bitline in said second subarray.
  - 22. The memory device of claim 16 wherein said plurality of gates are controlled by at least one control signal received from a source external to said memory device.
  - 23. The memory device of claim 16 and further comprising a first FIFO coupled to said first column decoder and a second FIFO coupled to said second column decoder.

24. A processing system comprising:
- a memory device including;
  
  a first subarray of memory cells arranged in rows and columns, each said column associated with a conductive bitline and each said row associated with a conductive wordline;
  
  a second subarray of memory cells arranged in rows and columns, each said column associated with a conductive bitline and each said row associated with a conductive wordline;
  
  circuitry for randomly accessing at least one selected cell in said first subarray;
  
  circuitry for randomly accessing at least one selected cell in said second subarray;
  
  circuitry for coupling a selected one of said bitlines of said first subarray with a selected one of said bitlines of said second subarray for transferring data from an accessed cell of said first subarray to an accessed cell of said second subarray;
  
  a first display device for displaying data received from said first subarray; and
  
  a second display device for displaying data received from said second subarray.
- View Dependent Claims (25, 26, 27)
- - 25. The processing system of claim 24 wherein said first and second display devices operate at different refresh rates.
  - 26. The processing system of claim 24 wherein said circuitry for accessing a said cell in said first subarray and said circuitry for accessing a said cell in said second subarray are coupled to a single display controller.
  - 27. The processing system of claim 24 wherein said circuitry for accessing a said cell in said first subarray and said circuitry for accessing a said cell in said second subarray are coupled to a single core logic chip set.

28. A method for performing a data transfer in a memory subsystem including a first subarray of memory cells arranged in rows and columns, each column associated with a conductive bitline and each row associated with a conductive wordline, a second subarray of memory cells arranged in rows and columns, each column associated with a conductive bitline and each row associated with a conductive wordline, and a plurality gates partitioned into at least two independently controllable groups, each group of gates for coupling selected ones of the bitlines of the first subarray with corresponding ones of the bitlines of said second subarray, the method comprising the steps of:
- activating a selected wordline in the first subarray;
  
  sensing data at the bitlines of the first subarray from the cells of the selected row;
  
  activating a selected group of the gates to couple the sensed data from ones of the bitlines of the first subarray to selected ones of the bitlines of the second subarray; and
  
  activating a selected wordline of the second subarray to write the data from the first subarray into cells of a selected row and the columns associated with the selected bitlines of the second subarray.
- View Dependent Claims (29, 30)
- - 29. The method of claim 28 and further comprising the step of latching the data at the bitlines of the first subarray after said step of sensing.
  - 30. The method of claim 28 and further comprising the step of deactivating the selected wordline in the first subarray prior to said step of activating the selected wordline in the second subarray.

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Current Assignee
Intellectual Ventures II LLC (Intellectual Ventures LLC)
Original Assignee
Cirrus Logic Incorporated
Inventors
Rao, G. R. Mohan
Primary Examiner(s)
Dinh, Son T.

Application Number

US08/548,752
Time in Patent Office

747 Days
Field of Search

365/230.03, 365/149, 365/221, 365/230.04
US Class Current

365/230.03
CPC Class Codes

G11C 7/18 Bit line organisation; Bit ...

Multiple-bank memory architecture and systems and methods using the same

First Claim

4 Assignments

Litigations

1 Petition

Reexamination

Accused Products

Abstract

35 Citations

30 Claims

Specification

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Multiple-bank memory architecture and systems and methods using the same

First Claim

4 Assignments

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Litigations

1 Petition

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Reexamination

Accused Products

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Abstract

35 Citations

30 Claims

Specification

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