Integrated circuit chip with adaptive input-output port
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First Claim
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1. An integrated circuit chip comprising:
- at least one adaptive input-output port, said port comprising;
an input buffer;
a controllable impedance arrangement coupled to said buffer and to at least two power supplies, said impedance arrangement for coupling to a communication line for transmitting and receiving data signals over said line; and
said controllable impedance arrangement for transmitting a data signal in a particular logic state by providing a corresponding particular impedance between at least one of said power supplies and said communication line, and for providing another particular impedance corresponding to a terminating impedance between at least one of said power supplies and said line when receiving a data signal over said line.
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Abstract
A controllable impedance arrangement is used in an adaptable input-output port of an integrated circuit configuration to enable the port to advantageously adapt its impedance according to whether its transmitting or receiving a communication signal. The controllable impedance arrangement provides different specific impedances for transmitting signals at respective signal levels, or a terminating impedance when receiving a data signal. This impedance arrangement enables the input-output port and corresponding integrated circuit to have compact dimensions relative to conventional integrated circuits.
94 Citations
10 Claims
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1. An integrated circuit chip comprising:
at least one adaptive input-output port, said port comprising; an input buffer; a controllable impedance arrangement coupled to said buffer and to at least two power supplies, said impedance arrangement for coupling to a communication line for transmitting and receiving data signals over said line; and said controllable impedance arrangement for transmitting a data signal in a particular logic state by providing a corresponding particular impedance between at least one of said power supplies and said communication line, and for providing another particular impedance corresponding to a terminating impedance between at least one of said power supplies and said line when receiving a data signal over said line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
Specification
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Litigation Data
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Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
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Original AssigneeLucent Technologies, Inc. (Nokia Corporation)
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InventorsGabara, Thaddeus John
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Primary Examiner(s)Hudspeth, David R.
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Application NumberUS08/672,494Time in Patent Office636 DaysField of Search326/21, 326/26, 326/27, 326/30, 326/37, 326/82, 326/86US Class Current326/30CPC Class CodesH04L 25/0278 Arrangements for impedance ...H04L 25/028 Arrangements specific to th...H04L 25/0292 Arrangements specific to th...
