Multi-threaded FIFO pool buffer and bus transfer control system
DC
First Claim
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1. A bus transfer control system for managing the transfer of multiple continuous asynchronous data streams, said bus transfer control system comprising:
- a) a buffer pool, definable as a plurality of memory buffers, capable of storing a plurality of data stream segments representing one or more data streams;
b) a plurality of data transfer devices coupled to said buffer pool and to a plurality of memory spaces, said data transfer devices supporting the iterative transfer of data stream segments between said memory buffers and said memory spaces, said data transfer devices providing requests for data stream segment transfers in response to the accessibility of said memory spaces to receive and provide data stream segments; and
c) a transfer controller, responsive to said requests and providing storage for status information as bus transfer units that define respective data streams, said transfer controller iteratively scanning said bus transfer units to select a first bus transfer unit and enable the transfer of a first predetermined data stream segment between said buffer pool and a first data transfer device specified by said first bus transfer unit in a predetermined scan iteration.
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Abstract
A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.
204 Citations
12 Claims
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1. A bus transfer control system for managing the transfer of multiple continuous asynchronous data streams, said bus transfer control system comprising:
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a) a buffer pool, definable as a plurality of memory buffers, capable of storing a plurality of data stream segments representing one or more data streams; b) a plurality of data transfer devices coupled to said buffer pool and to a plurality of memory spaces, said data transfer devices supporting the iterative transfer of data stream segments between said memory buffers and said memory spaces, said data transfer devices providing requests for data stream segment transfers in response to the accessibility of said memory spaces to receive and provide data stream segments; and c) a transfer controller, responsive to said requests and providing storage for status information as bus transfer units that define respective data streams, said transfer controller iteratively scanning said bus transfer units to select a first bus transfer unit and enable the transfer of a first predetermined data stream segment between said buffer pool and a first data transfer device specified by said first bus transfer unit in a predetermined scan iteration. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A bus master data transfer control system for transferring data segments of multiple continuous transfer data streams between a memory accessible by said bus master data transfer control system over an arbitrated access data transfer bus and a buffer pool, said bus master data transfer control system comprising:
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a) a buffer pool providing for the storage of a plurality of data packets; b) a first bus master unit coupleable to a first arbitrated access data transfer bus that provides access to a first external memory space, said first bus master unit providing for the transfer of a first predetermined data packet between said first arbitrated access data transfer bus and a first bus master data packet buffer and between said first bus master data packet buffer and said buffer pool; c) a second bus master unit coupleable to an second arbitrated access data transfer bus that provides access to a second external memory space, said second bus master unit providing for the transfer of a second predetermined data packet between said second arbitrated access data transfer bus and a second bus master data packet buffer and between said second bus master data packet buffer and said buffer pool; and d) a bus transfer controller, responsive to the data segment present statuses of said first and second bus master data packet buffers, including a table for storing bus transfer control units including first and second predetermined bus transfer control units that respectively determine bus master data transfers by said first and second bus master units relative to said buffer pool, said bus transfer controller iteratively operative to select a prioritized bus transfer control unit from said table to enable a bus data transfer relative to said buffer pool. - View Dependent Claims (8, 9, 10, 11)
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12. An I/O channel controller supporting the asynchronous transfer of a plurality of continuous transfer data streams between a memory and a plurality of I/O interface units, said I/O channel controller comprising:
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a) a FIFO pool buffer including a plurality of dynamically allocable FIFO buffers through which streams of data are asynchronously transferred; b) a plurality of I/O interface units; and c) a transfer control unit providing for the storage of one or more transfer control data units, said transfer control unit autonomously monitoring the amount of data buffered by any of said dynamically allocable FIFO buffers relative to a predetermined threshold amount and for selectively initiating the transfer of portions of said streams of data as defined by respective ones of said transfer control data units between said memory and said FIFO pool buffer.
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Specification
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Litigation Data
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Current AssigneeAltera Corporation (Intel Corporation)
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Original AssigneeDiamond Multimedia Systems Incorporated (SONICblue Incorporated)
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InventorsLewis, Adrian, Begur, Sridhar, Kilbourn, Thomas E., Spencer, Donald J., Gochnauer, Daniel B., Gifford, James K.
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Primary Examiner(s)Sheikh, Ayaz R.
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Assistant Examiner(s)PANCHOLI, JIGAR K
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Application NumberUS08/614,659Time in Patent Office860 DaysField of Search395/290, 395/308, 395/309, 395/250, 395/200.05, 395/872, 395/877, 395/200.61, 395/200.62, 395/200.63US Class Current710/52CPC Class CodesG06F 13/124 where hardware is a sequent...G06F 9/3879 for non-native instruction ...
