Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information

US 5,801,958 A
Filed: 09/10/1996
Issued: 09/01/1998
Est. Priority Date: 04/06/1990
Status: Expired due to Fees

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First Claim

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1. An interactive system for hierarchical display of control and dataflow information, on a system including a computer processor, information storage means, and graphical display means, comprising:

a design description entry device for a user to enter a high-level design description on said system, wherein said design description is stored on said information storage means;

an analyzer for analysis of the high-level design description, identification of modules according to a first predetermined criteria, and organization of said modules according to a second predetermined criteria;

a synthesizer for synthesizing one or more detailed electronic designs from the high-level design description;

a graphical control indicator for graphically representing control and data flow between graphical objects representing modules on said graphical display means, said graphical control and data flow indications representing control and data flow between the modules represented by the graphical objects;

a selector for selecting a level of hierarchical abstraction for any displayed graphical object; and

an indicator for indicating that a displayed graphical object represents a module having progeny modules associated therewith at a lower level of abstraction.

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Abstract

A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "modules" of the design and design hierarchy. The user can specify a level of detail to be displayed for any design element or group of design elements. Any CDFG (control and dataflow graph) object can be "annotated" with a visual attribute or with text to indicate information about the design elements represented by the object. For example, block size, interior color, border color, line thickness, line style, etc., can be used to convey quantitative or qualitative information about a CDFG object. Examples of information which can be used to "annotate" objects include power dissipation, propagation delay, the number of HDL statement represented, circuit area, number of logic gates, etc. The user is able to expand and/or compress CDFG blocks either "in-place" on a higher level CDFG display or to be displayed in isolation. Simulation-related data can also be used to annotate the CDFG. By viewing CDFG'"'"'s (particularly annotated CDFG'"'"'s) for a variety of trial designs, a problem-solving user can gain quick insight into the effects and effectiveness of various design choices.

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40 Claims

1. An interactive system for hierarchical display of control and dataflow information, on a system including a computer processor, information storage means, and graphical display means, comprising:
- a design description entry device for a user to enter a high-level design description on said system, wherein said design description is stored on said information storage means;
  
  an analyzer for analysis of the high-level design description, identification of modules according to a first predetermined criteria, and organization of said modules according to a second predetermined criteria;
  
  a synthesizer for synthesizing one or more detailed electronic designs from the high-level design description;
  
  a graphical control indicator for graphically representing control and data flow between graphical objects representing modules on said graphical display means, said graphical control and data flow indications representing control and data flow between the modules represented by the graphical objects;
  
  a selector for selecting a level of hierarchical abstraction for any displayed graphical object; and
  
  an indicator for indicating that a displayed graphical object represents a module having progeny modules associated therewith at a lower level of abstraction.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- - 2. A system according to claim 1, wherein identification and organization of modules is accomplished in a hierarchical manner by the analyzer such that:
    - each module at other than a highest level of abstraction is associated with ancestor modules at higher levels of abstraction; and
      
      each module at other than a lowest level of abstraction is associated with progeny modules at lower levels of abstraction.
  - 3. A system according to claim 1, further comprising:
    - a graphical object selector for selecting a graphical object representing a module; and
      
      an object and flow display device for displaying progeny graphical objects and control and data flow between said progeny graphical objects, said progeny graphical objects representing progeny modules of the module represented by the selected graphical object.
  - 4. A system according to claim 3, further comprising:
    - an isolator for displaying the progeny graphical objects in isolation.
  - 5. A system according to claim 4, wherein the information related to the module is a set of HDL code statement represented by the module.
  - 6. A system according to claim 3, further comprising:
    - a graphical objects progeny display device for displaying the progeny graphical objects in place of the selected graphical object.
  - 7. A system according to claim 1, further comprising:
    - an annotator for annotating any graphical object with information related to the module represented by the object.
  - 8. A system according to claim 7, wherein the annotator controls at least one visual attributes of the graphical object.
  - 9. A method according to claim 8, wherein said annotating step controls at least one visual attributes of the graphical object.
  - 10. A method according to claim 8, wherein said annotating step provides textual information adjacent to the graphical object.
  - 11. A method according to claim 8, wherein the information related to the module is simulation-related information.
  - 12. A method according to claim 8, wherein the information related to the module describes one or more physical characteristics of one or more circuit elements represented by the module.
  - 13. A system according to claim 7, wherein the annotator provides textual information adjacent to the graphical object.
  - 14. A system according to claim 7, wherein the information related to the module is simulation-related information.
  - 15. A system according to claim 7, wherein the information related to the module describes one or more physical characteristics of one or more circuit elements represented by the module.

16. A method of creating and validating a structural description of an electronic system from a higher level, behavior-oriented description thereof on an interactive system, comprising the steps of:
- entering a high-level design description on said system;
  
  storing said design description on said information storage means;
  
  analyzing the high-level design description;
  
  identifying modules according to a first predetermined criteria;
  
  organizing said modules according to a second predetermined criteria;
  
  synthesizing one or more detailed electronic designs from the high-level design description;
  
  graphically representing control and data flow between graphical objects representing modules on said graphical display means, said graphical control and data flow indications representing control and data flow between the modules represented by the graphical objects;
  
  selecting a level of hierarchical abstraction for any displayed graphical object; and
  
  providing an indication that a displayed graphical object represents a module having progeny modules associated therewith at a lower level of abstraction.
- View Dependent Claims (17, 18, 19, 20, 21, 22)
- - 17. A method according to claim 16, wherein said identifying and organizing steps are accomplished such that:
    - each module at other than a highest level of abstraction is associated with ancestor modules at higher levels of abstraction; and
      
      each module at other than a lowest level of abstraction is associated with progeny modules at lower levels of abstraction.
  - 18. A method according to claim 17, further comprising:
    - selecting a graphical object representing a module; and
      
      displaying progeny graphical objects and control and data flow between said progeny graphical objects, said progeny graphical objects representing progeny modules of the module represented by the selected graphical object.
  - 19. A method according to claim 18, further comprising:
    - displaying the progeny graphical objects in isolation.
  - 20. A method according to claim 19, wherein the information related to the module is a set of HDL code statement represented by the module.
  - 21. A method according to claim 18, further comprising:
    - displaying the progeny graphical objects in place of the selected graphical object.
  - 22. A method according to claim 16, further comprising:
    - annotating any graphical object with information related to the module represented by the object.

23. A method of creating and validating a structural description of a system from a higher level, behavior-oriented description thereof, comprising the steps of:
- entering a specification for a design of desired behavior of the system in a high-level, behavior-oriented language;
  
  iteratively simulating and changing the design of the system at the behavioral-level until the desired behavior is obtained;
  
  partitioning the design of the system into a number of architectural blocks and constraining the architectural choices to those which meet the high-level timing goals;
  
  directing the various architectural blocks to logic synthesis programs, thereby providing a netlist or gate-level description of the design;
  
  organizing design objects associated with said architectural blocks in a predetermined hierarchical manner; and
  
  displaying at least a portion of the system design as a plurality of graphical objects.
- View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
- - 24. A method according to claim 23, wherein said design of desired behavior of the electronic system includes high-level timing goals.
  - 25. A method according to claim 23, wherein said organizing in a predetermined hierarchical manner step is where:
    - each design object at other than a highest level of abstraction is associated with ancestor design objects at higher levels of abstraction; and
      
      each design object at other than a lowest level of abstraction is associated with progeny design objects at lower levels of abstraction.
  - 26. A method according to claim 23, wherein said displaying step further comprises associating each graphical object with one or more respective design objects, said graphical objects interconnected with control and data flow indications to form a control and dataflow graph.
  - 27. A method according to claim 23, further comprising the step of:
    - annotating at least some of the graphical objects with information related to graphical objects representing the design objects.
  - 28. A method according to claim 23, wherein the graphical objects are annotated by changing at least one visual attribute thereof.
  - 29. A method according to claim 23, wherein the graphical objects are annotated with textual information.
  - 30. A method according to claim 23, wherein the information related to the design objects includes simulation-related data.
  - 31. A method according to claim 23, wherein the information related to the design objects describes one or more physical characteristics of circuit elements represented by the design objects.

32. A method of creating an electronic design on a system having an accessible database, design tools, and a display device and one or more input devices enabling a user to interact with the system, comprising:
- displaying a control and dataflow graph representation of an electronic design, the control and dataflow graph being at a given hierarchical level of abstraction;
  
  storing in the accessible database information relating to the electronic design at various levels of abstraction;
  
  retrieving information relating to the electronic design from the accessible database;
  
  displaying the information contemporaneously with displaying the control and dataflow graph; and
  
  providing selectable representations of objects represented in the control and dataflow graph.
- View Dependent Claims (33, 34, 35, 36, 37, 38)
- - 33. A method according to claim 32, wherein said selectable representations are at a lower level.
  - 34. A method according to claim 32, further comprising:
    - displaying the representations of the objects contemporaneously with displaying the control and dataflow graph.
  - 35. A method according to claim 33, further comprising:
    - displaying the representations of the objects in isolation of the control and dataflow graph in the form of a lower-level control and dataflow graph.
  - 36. A method according to claim 35, further comprising:
    - annotating at least one object in the control and dataflow graph with information related to the object.
  - 37. A method according to claim 36, wherein the annotation of the at least one object is accomplished by altering a visual attribute of the object.
  - 38. A method according to claim 37, wherein the annotation of the at least one object is accomplished by providing descriptive textual information adjacent to the at least one objection on the display device.

39. A method of creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising:
- entering a specification for a design of desired behavior of a device, including high-level timing goals, in a high-level, behavior-oriented language;
  
  iteratively simulating and changing the design of the device at the behavioral-level until the desired behavior is obtained;
  
  partitioning the design of the device into a number of architect blocks which meet the high-level timing goals;
  
  displaying a control and data flow graph corresponding to the partitioned design; and
  
  directing the various architectural blocks to logic synthesis programs.
- View Dependent Claims (40)
- - 40. The method of claim 39, wherein said directing step provides a netlist or gate-level description of the design.

Specification

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Litigation Data

Current Assignee
LSI Logic Corporation (Broadcom, Inc.)
Original Assignee
LSI Logic Corporation (Broadcom, Inc.)
Inventors
Dangelo, Carlos, Watkins, Daniel, Mintz, Doron
Primary Examiner(s)
Trans, Vincent N.

Application Number

US08/707,918
Time in Patent Office

721 Days
Field of Search

364/488, 364/489, 364/490, 364/491
US Class Current

716/102
CPC Class Codes

G01R 31/31704   Design for test; Design ver...

G01R 31/318335   Test pattern compression or...

G01R 31/318357   Simulation computer simulat...

G01R 31/318364   as a result of hardware sim...

G06F 11/261   by simulating additional ha...

G06F 30/30   Circuit design

G06F 30/31   Design entry, e.g. editors ...

G06F 30/33   Design verification, e.g. f...

G06F 30/3308   using simulation

Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information

First Claim

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Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information

First Claim

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Accused Products

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Abstract

486 Citations

40 Claims

Specification

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Use Cases

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Others