High performance microprocessor having variable speed system clock
DC CAFC
First Claim
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1. A microprocessor system, comprising a single integrated circuit including a central processing unit and an entire ring oscillator variable speed system clock in said single integrated circuit and connected to said central processing unit for clocking said central processing unit, said central processing unit and said ring oscillator variable speed system clock each including a plurality of electronic devices correspondingly constructed of the same process technology with corresponding manufacturing variations, a processing frequency capability of said central processing unit and a speed of said ring oscillator variable speed system clock varying together due to said manufacturing variations and due to at least operating voltage and temperature of said single integrated circuit;
- an on-chip input/output interface connected to exchange coupling control signals, addresses and data with said central processing unit; and
a second clock independent of said ring oscillator variable speed system clock connected to said input/output interface.
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Abstract
A high performance, low cost microprocessor system having a variable speed system clock is disclosed herein. The microprocessor system includes an integrated circuit having a central processing unit and a ring oscillator variable speed system clock for clocking the microprocessor. The central processing unit and ring oscillator variable speed system clock each include a plurality of electronic devices of like type, which allows the central processing unit to operate at a variable processing frequency dependent upon a variable speed of the ring oscillator variable speed system clock. The microprocessor system may also include an input/output interface connected to exchange coupling control signals, address and data with the central processing unit. The input/output interface is independently clocked by a second clock connected thereto.
186 Citations
10 Claims
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1. A microprocessor system, comprising a single integrated circuit including a central processing unit and an entire ring oscillator variable speed system clock in said single integrated circuit and connected to said central processing unit for clocking said central processing unit, said central processing unit and said ring oscillator variable speed system clock each including a plurality of electronic devices correspondingly constructed of the same process technology with corresponding manufacturing variations, a processing frequency capability of said central processing unit and a speed of said ring oscillator variable speed system clock varying together due to said manufacturing variations and due to at least operating voltage and temperature of said single integrated circuit;
- an on-chip input/output interface connected to exchange coupling control signals, addresses and data with said central processing unit; and
a second clock independent of said ring oscillator variable speed system clock connected to said input/output interface. - View Dependent Claims (2)
- an on-chip input/output interface connected to exchange coupling control signals, addresses and data with said central processing unit; and
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3. In a microprocessor integrated circuit, a method for clocking the microprocessor within the integrated circuit, comprising the steps of:
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providing an entire ring oscillator system clock constructed of electronic devices within the integrated circuit, said electronic devices having operating characteristics which will, because said entire ring oscillator system clock and said microprocessor are located within the same integrated circuit, vary together with operating characteristics of electronic devices included within the microprocessor; using the ring oscillator system clock for clocking the microprocessor, said microprocessor operating at a variable processing frequency dependent upon a variable speed of said ring oscillator system clock; providing an on chip input/output interface for the microprocessor integrated circuit; and clocking the input/output interface with a second clock independent of the ring oscillator system clock. - View Dependent Claims (4, 5)
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6. A microprocessor system comprising:
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a central processing unit disposed upon an integrated circuit substrate, said central processing unit operating at a processing frequency and being constructed of a first plurality of electronic devices; an entire oscillator disposed upon said integrated circuit substrate and connected to said central processing unit, said oscillator clocking said central processing unit at a clock rate and being constructed of a second plurality of electronic devices, thus varying the processing frequency of said first plurality of electronic devices and the clock rate of said second plurality of electronic devices in the same way as a function of parameter variation in one or more fabrication or operational parameters associated with said integrated circuit substrate, thereby enabling said processing frequency to track said clock rate in response to said parameter variation; an on-chip input/output interface, connected between said said central processing unit and an external memory bus, for facilitating exchanging coupling control signals, addresses and data with said central processing unit; and an external clock, independent of said oscillator, connected to said input/output interface wherein said external clock is operative at a frequency independent of a clock frequency of said oscillator. - View Dependent Claims (7, 8, 9)
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10. In a microprocessor system including a central processing unit, a method for clocking said central processing unit comprising the steps of:
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providing said central processing unit upon an integrated circuit substrate, said central processing unit being constructed of a first plurality of transistors and being operative at a processing frequency; providing an entire variable speed clock disposed upon said integrated circuit substrate, said variable speed clock being constructed of a second plurality of transistors; clocking said central processing unit at a clock rate using said variable speed clock with said central processing unit being clocked by said variable speed clock at a variable frequency dependent upon variation in one or more fabrication or operational parameters associated with said integrated circuit substrate, said processing frequency and said clock rate varying in the same way relative to said variation in said one or more fabrication or operational parameters associated with said integrated circuit substrate; connecting an on chip input/output interface between said central processing unit and an external memory bus, and exchanging coupling control signals, addresses and data between said input/output interface and said central processing unit; and clocking said input/output interface using an external clock wherein said external clock is operative at a frequency independent of a clock frequency of said oscillator.
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Specification
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Litigation Data
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Current AssigneeCharles H. Moore
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Original AssigneePatriot Scientific Corporation
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InventorsMoore, Charles H., Fish, Russell H. III
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Primary Examiner(s)Eng, David Y.
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Application NumberUS08/484,918Time in Patent Office1,196 DaysField of Search395/500, 395/551, 395/555, 395/845US Class Current710/25CPC Class CodesG06F 12/0875 with dedicated cache, e.g. ...G06F 15/7832 on one IC chip (single chip...G06F 2207/581 Generating an LFSR sequence...G06F 2207/583 Serial finite field impleme...G06F 7/5272 with row wise addition of p...G06F 7/584 using finite field arithmet...G06F 7/785 having a sequence of storag...G06F 9/30 Arrangements for executing ...G06F 9/30036 Instructions to perform ope...G06F 9/30054 Unconditional branch instru...G06F 9/30065 Loop control instructions; ...G06F 9/30069 Instruction skipping instru...G06F 9/30145 Instruction analysis, e.g. ...G06F 9/30167 of immediate specifier, e.g...G06F 9/325 for loops, e.g. loop detect...G06F 9/3802 Instruction prefetchingG06F 9/3806 using address prediction, e...G06F 9/381 Loop bufferingG06F 9/3824 Operand accessingG06F 9/3867 using instruction pipelines
