Dynamic memory device with refresh circuit and refresh method
DC
First Claim
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1. A dynamic memory device comprising:
- (a) a plurality of storage elements;
(b) a signal provider for sending refresh signals to said storage elements and for providing addresses of substantially all storage elements; and
(c) a programmable signal controller coupled to said signal provider for receiving said addresses and for comparing magnitudes of said addresses to a magnitude of a reference address, said programmable signal controller for controlling said signal provider so that, during a particular refresh cycle in which addresses for substantially all storage elements are generated, only a first sub-set of storage elements with addresses in a first magnitude relation to said reference address are refreshed and a second sub-set of storage elements with addresses in a second magnitude relation to said reference address are not refreshed.
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Abstract
A refresh circuit (230) and a method for the refresh of dynamic memory devices (201) are described where the rows to be refreshed are determined by a logical function and by a reference address (223). The availability of refresh signals (215) for the rows at the outputs (217) of a decoder (214) is determined by control logic (224) which is connected to an address generator (212) and to a reference register (222) which contains a reference address (223). By supplying the reference address (223) to the refresh circuit (230) it is possible to determine which rows are to be refreshed. The memory array (210) of the dynamic memory device (201) can be refreshed partially and energy consumption for the refresh can be reduced.
50 Citations
13 Claims
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1. A dynamic memory device comprising:
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(a) a plurality of storage elements; (b) a signal provider for sending refresh signals to said storage elements and for providing addresses of substantially all storage elements; and (c) a programmable signal controller coupled to said signal provider for receiving said addresses and for comparing magnitudes of said addresses to a magnitude of a reference address, said programmable signal controller for controlling said signal provider so that, during a particular refresh cycle in which addresses for substantially all storage elements are generated, only a first sub-set of storage elements with addresses in a first magnitude relation to said reference address are refreshed and a second sub-set of storage elements with addresses in a second magnitude relation to said reference address are not refreshed.
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2. A dynamic memory device comprising:
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(a) a plurality of storage elements; (b) a signal provider for sending refresh signals to said storage elements; and (c) a programmable signal controller coupled to said signal provider for controlling said signal provider so that, during a particular refresh cycle, only a first sub-set of storage elements are refreshed and a second sub-set of storage elements are not refreshed, said signal provider having (i) an address generator for providing addresses for said storage elements; and (ii) a decoder for receiving said addresses from said address generator and, in response to a control signal received from said signal controller, sending refresh signals to said first sub-set of storage elements but not to said second sub-set of storage elements, said signal controller having a reference register for storing a reference address and control logic coupled to said reference register, to said address generator, and to said decoder, wherein said control logic uses said addresses generated by said address generator and said reference address to determine which storage elements are in said first sub-set and which storage elements are in said second sub-set. - View Dependent Claims (3, 4)
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5. A method for the refresh of dynamic memory devices having a plurality of rows with storage elements, comprising the steps of:
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a) storing a reference address; b) generating an address for one of said rows; c) relating said row address and said reference address by a logical function, thereby determining if a magnitude of said row address belongs to a first sub-set or a second sub-set of magnitudes of row addresses; d) sending refresh signals to said row only if said row address belongs to said first sub-set; and e) repeating said steps b) to d) for substantially all rows.
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6. A memory comprising:
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an array of rows; a generator which continuously generates row addresses; and a filter coupled between said generator and said array, said filter consecutively relating substantially all of said row addresses to a reference address and depending on a comparison between said reference address and said row addresses sending refresh signals to some of said rows and not sending refresh signals to the other rows.
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7. A memory comprising:
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an array of rows; a generator which continuously generates row addresses; and a filter coupled between said generator and said array, said filter consecutively relating substantially all of said row addresses to a reference address and sending refresh signals to some of said rows and not sending refresh signals to the other rows said filter having (a) a decoder receiving said row addresses and sending refresh signals, and (b) a comparator receiving said reference address once and said row addresses consecutively, said comparator enabling said decoder or disabling said decoder.
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8. An apparatus comprising:
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a plurality of n blocks Ai (i=1 to n), each block Ai being accessible by a single address ai ; a generator which in a single refresh cycle provides addresses ai from i=1 to i=n in any order; a register for storing a reference address; and a comparator receiving an address ai ; every time said comparator has received an address ai, comparing said address ai with said reference address, and every time said comparator has compared, selectively forwarding said address ai to Ai so that a refresh operation is executed in some of said n blocks, but not in all blocks Ai. - View Dependent Claims (9, 10)
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11. A dynamic memory comprising:
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a plurality of n rows Ai (i=1 to i=n) each having storage cells; a generator which cyclically generates addresses ai for i=1 to i=n; a decoder receiving one address ai at a time, said decoder being either enabled or disabled, said decoder when enabled sending a refresh signal to said storage cells of row Ai which is identified by said address ai ; and a control logic cyclically receiving addresses ai, and enabling or disabling said decoder depending on a logical relation between and a reference address ar. - View Dependent Claims (13)
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12. A dynamic memory comprising:
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a plurality of n rows Ai (i=1 to i=n) each having storage cells; a generator which cyclically generates addresses ai for i=1 to i=n; a decoder receiving one address ai at a time, said decoder being either enabled or disabled, said decoder when enabled sending a refresh signal to said storage cells of row Ai which is identified by said address ai ; and a control logic cyclically receiving addresses ai and enabling or disabling said decoder depending on a logical relation between ai and a reference address ai, said control logic enabling the decoder for ai <
ar and ai =ar and disabling said decoder for ai >
ar wherein r is a predetermined integer between from 0 to n.
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Specification
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Litigation Data
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Current AssigneeNorth Star Innovations Inc. (Wi-LAN Inc.)
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Original AssigneeMotorola, Inc. (Motorola Solutions, Inc.)
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InventorsBen-Zvi, Jacob
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Primary Examiner(s)Nelms, David
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Assistant Examiner(s)Ho, Hoai V.
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Application NumberUS08/976,835Time in Patent Office456 DaysField of Search365/222, 365/230.03, 365/185.11, 365/185.22US Class Current365/222CPC Class CodesG11C 11/406 Management or control of th...G11C 11/40622 Partial refresh of memory a...G11C 2211/4067 Refresh in standby or low p...
