Audio decoder employing error concealment technique

US 5,918,205 A
Filed: 01/30/1996
Issued: 06/29/1999
Est. Priority Date: 01/30/1996
Status: Expired due to Term

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1. A method of processing an encoded audio signal, comprising the steps of:

decoding the encoded signal into vector samples;

replacing those vector samples decoded when a concealment of an error is requested with neutral data;

after said replacing step, buffering the decoded vector samples; and

filtering the decoded vector samples to generate digital samples.

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Abstract

An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage (or after storage, if desired) in the Vector FIFO buffer when error concealment is performed.

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28 Claims

1. A method of processing an encoded audio signal, comprising the steps of:
- decoding the encoded signal into vector samples;
  
  replacing those vector samples decoded when a concealment of an error is requested with neutral data;
  
  after said replacing step, buffering the decoded vector samples; and
  
  filtering the decoded vector samples to generate digital samples.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- - 2. The method of claim 1, wherein the event is a processing error.
  - 3. The method of claim 2, wherein the event is caused by a CRC error.
  - 4. The method of claim 2, wherein the event is caused by a frame reconstruction error.
  - 5. The method of claim 2, wherein the event is caused by a decode error.
  - 6. The method of claim 1, wherein the encoded signal includes normalized DCT samples, and wherein the encoded signal is decoded by the steps including:
    - dequantizing the DCT samples;
      
      rescaling the dequantized DCT samples; and
      
      transforming the rescaled DCT samples to IDCT vector samples.
  - 7. The method of claim 1, wherein the vector samples are replaced by zeroing out the vector samples.
  - 8. The method of claim 7, wherein the vector samples are zeroed out by the steps includinggenerating a pulse having a width that coincides with the occurrence of the event;
    - andperforming at least one logic operation with the pulse and the vector samples.
  - 9. The method of claim 8, wherein the logic operation is performed by:
    - inverting the pulse; and
      
      AND'"'"'ing the pulse with the vector samples.
  - 10. The method of claim 1, wherein the vector samples are buffered in groups on a first-in, first-out basis.
  - 11. The method of claim 10, wherein the buffered vector samples are filtered by spreading out the buffered vector samples.
  - 12. The method of claim 10, wherein the buffered vector samples are filtered by performing the steps of:
    - storing each group of buffered vector samples in a window, whereby the groups are stored in separate windows;
      
      forming products of the windowed vector samples and filter coefficients; and
      
      summing the products together.
  - 13. The method of claim 1, further comprising the step of reconstructing an analog audio signal from contiguous digital samples.

14. A method of generating an analog audio signal in response to an MPEG-encoded signal, comprising the steps of:
- processing the MPEG-encoded audio signals into IDCT vector samples;
  
  replacing the vector samples with neutral data when an error concealment is requested;
  
  after said replacing step, buffering the IDCT vector samples in groups on a first-in, first-out basis; and
  
  reconstructing the audio signal from an output of the filter.
- View Dependent Claims (15)
- - 15. The method of claim 14, wherein the IDCT vector samples are replaced by zeroing out the IDCT vector samples.

16. An audio core module, comprising:
- a vector FIFO;
  
  a windowed polyphase filter having an input coupled to an output of the vector FIFO; and
  
  at least one gate for replacing data for the Vector FIFO buffer with neutral data when an error concealment is requested.
- View Dependent Claims (17, 18, 19, 20, 21, 22)
- - 17. The audio core module of claim 16, wherein an output of the at least one gate is coupled to an input of the vector FIFO, the at least one gate replacing data supplied to the input of the Vector FIFO with neutral data when the error concealment is requested.
  - 18. The audio core module of claim 17, wherein the at least one gate zeroes out the data provided to the input of the Vector FIFO buffer when the error concealment is requested.
  - 19. The audio core module of claim 17, wherein a Conceal signal is generated when the error concealment is requested;
    - and wherein the at least one gate outputs zeroed out data in response to the Conceal signal and the data provided to the input of Vector FIFO buffer.
  - 20. The audio core module of claim 19, wherein the Conceal signal is a pulse, and wherein the at least one gate includes an inverter for inverting the pulse an AND gate for AND'"'"'ing together the pulse and the data provided to the input of Vector FIFO buffer.
  - 21. The audio core module of claim 16, wherein the FIFO, the filter and the at least one gate are on a single chip.
  - 22. An MPEG audio decoder, comprising:
    - an audio host module;
      
      an audio output; and
      
      the audio core module of claim 20, the audio core module being coupled between the audio host module and the audio output, the audio core module generating a Conceal signal when the error concealment is requested, the audio core module replacing the data stored in the Vector FIFO buffer with the neutral data in response to the Conceal signal.

23. An audio core module comprising:
- means for decoding an encoded signal;
  
  means, responsive to the decoding means, for zeroing out the decoded signal when an error concealment is requested;
  
  means for buffering an output of the zeroing-out means; and
  
  means for filtering an output of the buffering means to produce samples that can be reconstructed into an analog audio signal.
- View Dependent Claims (24)
- - 24. The audio core module of claim 23, wherein the decoding means, the zeroing-out means, the buffering means, and the filtering means are on a single chip.

25. A method of performing an error concealment in an audio encoder, the method comprising the steps of:
- parsing an input bit stream to obtain Discrete Cosine Transform (DCT) vector samples;
  
  dequantizing, rescaling, and transforming the DCT vector samples to form Inverse Discrete Cosine Transform (IDCT) vector samples;
  
  replacing the IDCT vector samples with neutral data; and
  
  after the replacing, buffering the IDCT vector samples using a Vector FIFO buffer.
- View Dependent Claims (26, 27, 28)
- - 26. The method of claim 25, wherein the IDCT vector samples are replaced by being zeroed out.
  - 27. The method of claim 26, wherein the IDCT vector samples are zeroed out by the steps of:
    - generating a pulse; and
      
      performing at least one logic operation with the pulse and the vector samples.
  - 28. The method of claim 27, wherein the logic operation is performed by:
    - inverting the pulse; and
      
      AND'"'"'ing the pulse with the IDCT vector samples.

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Litigation Data

Current Assignee
Avago Technologies General IP PTE Limited (Broadcom, Inc.)
Original Assignee
LSI Logic Corporation (Broadcom, Inc.)
Inventors
Dierke, Gregg
Primary Examiner(s)
Dorvil, Richemond

Application Number

US08/595,225
Time in Patent Office

1,246 Days
Field of Search

395/2.92, 395/2.31, 395/2.09, 395/2.42, 395/2.39, 704/500, 704/501, 704/502, 704/503, 704/200, 704/222, 704/230, 704/229, 704/233
US Class Current

704/230
CPC Class Codes

G10L 19/005 Correction of errors induce...

Audio decoder employing error concealment technique

First Claim

8 Assignments

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Abstract

18 Citations

28 Claims

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Audio decoder employing error concealment technique

First Claim

8 Assignments

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Litigations

0 Petitions

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Accused Products

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Abstract

18 Citations

28 Claims

Specification

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