Flip chip bump distribution on die
DC
First Claim
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1. An arrangement of bump pads for use on a face of a semiconductor die having four edges, comprising:
- a plurality of corner regions, each corner region comprising a first plurality of input/output bump pads and a first plurality of power bump pads, said corner regions each adjoining two edges of said die;
a plurality of edge regions comprising a second plurality of input/output bump pads and a second plurality of power bump pads, said edge regions located along said four edges of said die and interleaved between said corner regions; and
a core power region comprising a third plurality of power bump pads, said power region centrally located on said face of said semiconductor die.
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Abstract
An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special "checkerboard" arrangement also provided. Connections between the bumps and the edge of the die surface are shown. According to a second embodiment, there is provided a die surface arrangement with two power bumps, one live voltage, or power, bump and one ground bump, and multiple I/O bumps, all bumps linearly aligned, with the ground and power bumps both located intermediate between the I/O bumps. The ground, power, and I/O bumps form an array, and this array is replicated linearly across the die surface forming a linear array arrangement having alternately directed redistribution traces. The die surface arrangement comprises multiple linear array arrangements interspersed with multiple linearly aligned core power bumps.
210 Citations
41 Claims
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1. An arrangement of bump pads for use on a face of a semiconductor die having four edges, comprising:
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a plurality of corner regions, each corner region comprising a first plurality of input/output bump pads and a first plurality of power bump pads, said corner regions each adjoining two edges of said die; a plurality of edge regions comprising a second plurality of input/output bump pads and a second plurality of power bump pads, said edge regions located along said four edges of said die and interleaved between said corner regions; and a core power region comprising a third plurality of power bump pads, said power region centrally located on said face of said semiconductor die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An arrangement of bumps for use on a flip-chip die, having four edges, comprising:
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a plurality of corner regions on said die, said corner regions each adjoining two edges of said die; a plurality of edge regions on said die located along said four edges of said die and interleaved between said corner regions; a core power region centrally located on said die; an array of bumps comprising at least one power bump and a plurality of input/output bumps with each successive bump having a greater distance from an edge of said flip-chip die and having a trace directed towards said edge. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A semiconductor assembly, comprising:
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(a) a semiconductor die having a face and a plurality of edges; and (b) an arrangement of bump pads on said face, said arrangement comprising; a plurality of corner regions, each said corner region including a first plurality of input/output bump pads and a first plurality of power bump pads, said corner regions each adjoining a different two of said edges of said die; a plurality of edge regions including a second plurality of input/output bump pads and a second plurality of power bump pads, said edge regions being located along different said edges of said die and interleaved between said corner regions; and a core power region including a third plurality of power bump pads, said core power region being centrally located on said face. - View Dependent Claims (22)
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23. A semiconductor assembly, comprising:
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(a) a semiconductor die having a face; and (b) an arrangement of bump pads on said face, said arrangement comprising; a plurality of bump pads at each corner region of said face; a plurality of bump pads at each edge region of said face, said edge regions being located along respective edges of said die and interleaved between said corner regions; and a plurality of bump pads at a core power region which is located centrally on said face; wherein said core power region bump pads are in a checkerboard arrangement with an odd number of rows and odd number of columns of said bump pads. - View Dependent Claims (24)
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25. A semiconductor assembly, comprising:
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(a) a semiconductor die having a face; (b) an arrangement of bump pads on said face, said arrangement comprising; a plurality of bump pads at each corner region of said face; a plurality of bump pads at each edge region of said face, said edge regions being located along respective edges of said die and interleaved between said corner regions; and a plurality of bump pads at a core power region which is located centrally on said face; and (c) a power ring on an edge of said face and connecting power and ground signals for said corner and edge regions and thereby providing power. - View Dependent Claims (26)
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27. A semiconductor assembly, comprising:
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(a) a semiconductor die having a face; and (b) an arrangement of bump pads on said face, said arrangement comprising; a plurality of bump pads at each corner region of said face; a plurality of bump pads at each edge region of said face, said edge regions being located along respective edges of said die and interleaved between said corner regions; and a plurality of bump pads at a core power region which is centrally located on said face; wherein said plurality of bump pads at each edge region includes a plurality of arrays of bump pads, each of said plurality of arrays comprising a plurality of input/output bump pads, a ground pad and a voltage bump pad. - View Dependent Claims (28, 29, 30)
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31. A die construction comprising:
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an integrated circuit; and an arrangement of bump pads on said integrated circuit, said arrangement comprising; a first signal bump pad having a first trace radiating in a first direction and connected to a first input/output cell; a second signal bump pad having a second trace radiating in a second direction and connected to a second input/output cell, said first trace and said second trace disposed on opposite sides of a first line defined by said first signal bump and said second signal bump; a first power bump pad having a third trace radiating in said first direction and connected to a first power bus; and a second power bump pad having a fourth trace radiating in said second direction and connected to a second power bus, said third trace and said fourth trace disposed on opposite sides of a second line defined by said first power bump and said second power bump; said first signal bump pad disposed closer to a center of said integrated circuit than said second signal bump pad, said second signal bump pad disposed closer to said center of said integrated circuit than said first power bump pad, and said second signal bump pad disposed closer to said center of said integrated circuit than said second power bump. - View Dependent Claims (32, 33, 34, 35)
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36. A die construction comprising:
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an integrated circuit; a first power bus; a second power bus; and an arrangement of bump pads on said integrated circuit, said arrangement comprising; a first signal bump pad having a first trace radiating in a first direction and connected to a first input/output cell; a second signal bump pad having a second trace radiating in a second direction and connected to a second input/output cell, said first trace and said second trace disposed on opposite sides of a first line defined by said first signal bump and said second signal bump; a third signal bump pad having a third trace radiating in said first direction and connected to a third input/output cell; a fourth signal bump pad having a fourth trace radiating in said second direction and connected to a fourth input/output cell, said third trace and said fourth trace disposed on opposite sides of a second line defined by said third signal bump and said fourth signal bump; a first power bump pad connected to said first power bus; a second power bump pad connected to said second power bus; said first and second signal bumps disposed on an opposite side of said first power bus from said third and fourth signal bumps; said first signal bump pad disposed farther from said first power bus than said second signal bump pad, said fourth signal bump pad disposed farther from said first power bus than said third signal bump pad. - View Dependent Claims (37, 38, 39, 40)
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41. A pad arrangement for use on a flip-chip die, comprising:
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at least one power bump; a linearly aligned plurality of input/output bumps, wherein said linearly aligned plurality of input/output bumps are aligned with said at least one power bump; said at least one power bump is intermediate among said linearly aligned plurality of input/output bumps; said at least one power bump and said linearly aligned plurality of input/output bumps form an array, wherein said array is replicated linearly across said flip-chip die, thereby forming a linear bump array arrangement.
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Specification
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Litigation Data
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Current AssigneeBell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
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Original AssigneeLSI Logic Corporation (Broadcom, Inc.)
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InventorsLiang, Mike
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Primary Examiner(s)Arroyo, Teresa M.
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Application NumberUS08/747,325Time in Patent Office1,036 DaysField of Search257/786, 257/778, 257/691, 174/52.4US Class Current257/778CPC Class CodesH01L 2224/05599 MaterialH01L 2224/45099 MaterialH01L 2224/85399 MaterialH01L 23/50 for integrated circuit devi...H01L 24/05 of an individual bonding areaH01L 2924/00014 the subject-matter covered ...H01L 2924/01005 Boron [B]H01L 2924/01006 Carbon [C]H01L 2924/01014 Silicon [Si]H01L 2924/01033 Arsenic [As]H01L 2924/01082 Lead [Pb]H01L 2924/014 Solder alloysH01L 2924/14 Integrated circuitsH01L 2924/15173 in a single layer of the mu...H01L 2924/30107 Inductance
