Embedded enhanced DRAM, and associated method
DCFirst Claim
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1. An integrated circuit having a substrate, said integrated circuit comprising:
- at least one DRAM (dynamic random access memory) bank disposed at the substrate, said at least one DRAM bank formed of rows and columns of DRAM memory locations and defining a local memory array;
an SRAM (static random access memory) associated with each of said at least one DRAM bank and disposed at the substrate at which said at least one DRAM bank is also disposed, each SRAM formed of at least a row of SRAM memory locations and capable of caching data of at least a portion of a row of the DRAM memory locations with which the SRAM is associated; and
a logic element disposed at the substrate at which said at least one DRAM bank and said SRAM associated therewith are also disposed, said logic element having a first logic portion and a second logic portion, said first logic portion coupled to said at least one DRAM and to said SRAM associated therewith and operable to control access to the DRAM memory locations and the SRAM memory locations thereof, said second logic portion operable to request access to selected memory locations of said at least one DRAM and said SRAM associated therewith of to process data read therefrom.
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Abstract
An integrated circuit device, and an associated method, in which a logic element, such as a central processing unit, is embedded together with an EDRAM EDRAM (Enhanced Dynamic Random Access Memory) upon a common substrate die. A memory bus interconnects the EDRAM and the logic element. Data thruput rates of memory read and write operations are permitted to be of increased rates relative to the rates permitted of conventional, discrete devices.
47 Citations
22 Claims
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1. An integrated circuit having a substrate, said integrated circuit comprising:
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at least one DRAM (dynamic random access memory) bank disposed at the substrate, said at least one DRAM bank formed of rows and columns of DRAM memory locations and defining a local memory array; an SRAM (static random access memory) associated with each of said at least one DRAM bank and disposed at the substrate at which said at least one DRAM bank is also disposed, each SRAM formed of at least a row of SRAM memory locations and capable of caching data of at least a portion of a row of the DRAM memory locations with which the SRAM is associated; and a logic element disposed at the substrate at which said at least one DRAM bank and said SRAM associated therewith are also disposed, said logic element having a first logic portion and a second logic portion, said first logic portion coupled to said at least one DRAM and to said SRAM associated therewith and operable to control access to the DRAM memory locations and the SRAM memory locations thereof, said second logic portion operable to request access to selected memory locations of said at least one DRAM and said SRAM associated therewith of to process data read therefrom. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for accessing data, said method comprising the steps of:
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generating a first access request for accessing data stored at memory locations of a first memory row, the memory locations of the first memory row disposed upon a substrate; accessing the data stored at the memory locations identified in the first access request; while the data stored at the memory locations identified by the first access request is being accessed, generating a second access request for accessing data stored at memory locations of a second memory row, the memory locations of the second memory row upon the substrate at which the memory locations of the first memory row are also disposed; and accessing the data stored at the memory locations identified in is the second access request. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification