Embedded enhanced DRAM, and associated method

US 5,963,481 A
Filed: 06/30/1998
Issued: 10/05/1999
Est. Priority Date: 06/30/1998
Status: Expired due to Term

- Alert
- Pin

Associated Cases

Associated Defendants

First Claim

Patent Images

1. An integrated circuit having a substrate, said integrated circuit comprising:

at least one DRAM (dynamic random access memory) bank disposed at the substrate, said at least one DRAM bank formed of rows and columns of DRAM memory locations and defining a local memory array;

an SRAM (static random access memory) associated with each of said at least one DRAM bank and disposed at the substrate at which said at least one DRAM bank is also disposed, each SRAM formed of at least a row of SRAM memory locations and capable of caching data of at least a portion of a row of the DRAM memory locations with which the SRAM is associated; and

a logic element disposed at the substrate at which said at least one DRAM bank and said SRAM associated therewith are also disposed, said logic element having a first logic portion and a second logic portion, said first logic portion coupled to said at least one DRAM and to said SRAM associated therewith and operable to control access to the DRAM memory locations and the SRAM memory locations thereof, said second logic portion operable to request access to selected memory locations of said at least one DRAM and said SRAM associated therewith of to process data read therefrom.

View all claims

11 Assignments

Timeline View

Assignment View

Litigations

0 Petitions

Accused Products

Abstract

An integrated circuit device, and an associated method, in which a logic element, such as a central processing unit, is embedded together with an EDRAM EDRAM (Enhanced Dynamic Random Access Memory) upon a common substrate die. A memory bus interconnects the EDRAM and the logic element. Data thruput rates of memory read and write operations are permitted to be of increased rates relative to the rates permitted of conventional, discrete devices.

47 Citations

View as Search Results

22 Claims

1. An integrated circuit having a substrate, said integrated circuit comprising:
- at least one DRAM (dynamic random access memory) bank disposed at the substrate, said at least one DRAM bank formed of rows and columns of DRAM memory locations and defining a local memory array;
  
  an SRAM (static random access memory) associated with each of said at least one DRAM bank and disposed at the substrate at which said at least one DRAM bank is also disposed, each SRAM formed of at least a row of SRAM memory locations and capable of caching data of at least a portion of a row of the DRAM memory locations with which the SRAM is associated; and
  
  a logic element disposed at the substrate at which said at least one DRAM bank and said SRAM associated therewith are also disposed, said logic element having a first logic portion and a second logic portion, said first logic portion coupled to said at least one DRAM and to said SRAM associated therewith and operable to control access to the DRAM memory locations and the SRAM memory locations thereof, said second logic portion operable to request access to selected memory locations of said at least one DRAM and said SRAM associated therewith of to process data read therefrom.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- - 2. The integrated circuit of claim 1 wherein said at least one DRAM bank comprises a first DRAM bank and at least a second DRAM bank.
  - 3. The integrated circuit of claim 2 wherein said SRAM associated with each of said DRAM banks comprises a first SRAM associated with said first DRAM bank and at least a second SRAM associated with said at least second DRAM bank.
  - 4. The integrated circuit of claim 3 wherein the first logic portion of said logic element is operable to cause, during overlapping time periods, data to be read from a first selected row of memory locations, loaded from a selected one of said first and at least second DRAM bank into said SRAM associated therewith, and to cause data to be written to a second selected row of a selected one of said first and at least second DRAM bank.
  - 5. The integrated circuit of claim 4 wherein said logic element is operable to cause data to be read from the first selected row of memory locations loaded from said first DRAM bank, and to cause data to be written to the second selected row of said second DRAM bank.
  - 6. The integrated circuit of claim 4 wherein said logic element is operable to case data to be read from the first selected row of memory locations loaded from said first DRAM bank, and to cause data to be written to the second selected row of said first DRAM bank.
  - 7. The integrated circuit of claim 3 wherein the first logic portion of said logic element is operable to cause access to a first selected row and a second selected row of a selected one of said first and at least second DRAM bank during at least overlapping time periods, the first selected row forming a read row from which to read data and the second selected row forming a write row from which to write data during the overlapping time periods.
  - 8. The integrated circuit of claim 1 wherein the first logic portion of said logic element is operable to cause first data stored in a first row of said DRAM to be cached at said SRAM associated therewith, to cause second data to be written to a second row of said DRAM, and thereafter to cause the first data to be read from said SRAM.
  - 9. The integrated circuit of claim 1 wherein, when the first logic portion of said logic element accesses selected memory locations of said at least one DRAM bank, data stored in a row of the local memory array defined by said at least one DRAM bank containing the selected memory locations is loaded into said SRAM associated with said at least one DRAM bank, the data loaded into said SRAM thereafter to be read therefrom to be processed by the second logic portion of said logic element.
  - 10. The integrated circuit of claim 9 wherein the first logic portion is further operable to cause said at least one DRAM bank from which the data is loaded into said SRAM to be closed and precharged.
  - 11. The integrated circuit of claim 10 wherein the first logic portion is further operable to cause said at least one DRAM bank to be precharged at least partially concurrently with reading of the data loaded into said SRAM.
  - 12. The integrated circuit of claim 11 further comprising a memory bus interconnecting said logic element and said SRAM, and wherein the first logic portion of said logic element is further operable to monitor data transmission on said memory bus.
  - 13. The integrated circuit of claim 12 wherein the first logic portion of said logic element comprises a look-ahead controller operable to anticipate subsequent read requests of the second logic portion, the read requests identifying the memory locations at which data to be read is stored.
  - 14. The integrated circuit of claim 13 wherein said look-ahead controller comprising the first logic portion of said logic element generates row address selected signals, values of the row address selected signals identifying rows in which the selected memory locations are formed.
  - 15. The integrated circuit of claim 1 wherein the second logic portion of said logic element comprises a digital processing unit forming a computer central processing unit.

16. A method for accessing data, said method comprising the steps of:
- generating a first access request for accessing data stored at memory locations of a first memory row, the memory locations of the first memory row disposed upon a substrate;
  
  accessing the data stored at the memory locations identified in the first access request;
  
  while the data stored at the memory locations identified by the first access request is being accessed, generating a second access request for accessing data stored at memory locations of a second memory row, the memory locations of the second memory row upon the substrate at which the memory locations of the first memory row are also disposed; and
  
  accessing the data stored at the memory locations identified in is the second access request.
- View Dependent Claims (17, 18, 19, 20, 21, 22)
- - 17. The method of claim 16 wherein the first memory row identified by the first access request generated during said step of generating the first access request is located at a selected one of a first and at least a second DRAM (dynamic random access memory) bank.
  - 18. The method of claim 17 wherein the first access request generated during said step of generating the first access request is generated by a processing unit disposed upon a substrate common to the first and the at least second DRAM.
  - 19. The method of claim 18 wherein said step of accessing the data stored at the memory locations identified in the first access request comprises:
    - loading the data stored at the selected one of the first and the at least second DRAM into an SRAM (Static Random Access Memory) associated therewith, the SRAM disposed upon the substrate common to the processing unit and the first and the at least second DRAM; and
      
      reading the data loaded into the SRAM to the processing unit.
  - 20. The method of claim 19 wherein the second memory row identified by the second access request generated during said step of generating the second access request is located at a selected one of the first and the at least second DRAM bank.
  - 21. The method of claim 20 wherein the second access request generated during said step of generating the second access request is generated by the processing unit.
  - 22. The method of claim 20 wherein said step of accessing the data stored at the memory locations identified in the second access request comprises:
    - loading the data stored at the selected one of the first and the at least second DRAM into an SRAM associated therewith; and
      
      reading the data loaded into the SRAM to the processing unit.

Specification

Resources

Litigation Campaign Assessment

Litigation Data

Current Assignee
Complex Memory LLC (IPValuation Partners, LLC)
Original Assignee
Enhanced Memory Systems Incorporated (Infineon Technologies AG)
Inventors
Peters, Michael, Alwais, Michael
Primary Examiner(s)
Nelms, David
Assistant Examiner(s)
Lam, David

Application Number

US09/108,089
Time in Patent Office

462 Days
Field of Search

365/189.04, 365/198, 365/203, 395/425, 711/137
US Class Current

365/189.04
CPC Class Codes

G06F 12/0215   with look ahead addressing ...

G06F 12/0893   Caches characterised by the...

G06F 15/786   using a single memory module

G11C 11/005   comprising combined but ind...

G11C 7/22   Read-write [R-W] timing or ...

Embedded enhanced DRAM, and associated method

First Claim

11 Assignments

Litigations

0 Petitions

Accused Products

Abstract

47 Citations

22 Claims

Specification

Use Cases

Quick Links

Others

Embedded enhanced DRAM, and associated method

First Claim

11 Assignments

Subscription Required

Subscription Required

Litigations

0 Petitions

Subscription Required

Accused Products

Subscription Required

Abstract

47 Citations

22 Claims

Specification

Subscription Required

Use Cases

Quick Links

Others