Silicided shallow junction transistor formation and structure with high and low breakdown voltages
DC CAFC
First Claim
1. In an integrated circuit in and on a silicon substrate having an active region including a field effect transistor with a source and a drain and a gate, all of which a conductive contact is made comprising:
- a single crystalline silicon substrate with a upper surface region;
a shallow junction for each of the source and drain of the transistor underlying said upper surface of the silicon substrate;
a metal silicide layer having a lower surface disposed adjacent the shallow junction of each of the source and drain in the silicon substrate and above said upper surface of the silicon substrate; and
an epitaxial silicon layer disposed between said upper silicon surface and said lower surface of metal silicide and adjacent the shallow junction of each of the source and drain whereby the metal silicide does not extend below the upper silicon surface and encroach upon the shallow junction of each of the source and the drain.
2 Assignments
Litigations
1 Petition
Accused Products
Abstract
A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction in a single crystal substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with all of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and more conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.
20 Citations
13 Claims
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1. In an integrated circuit in and on a silicon substrate having an active region including a field effect transistor with a source and a drain and a gate, all of which a conductive contact is made comprising:
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a single crystalline silicon substrate with a upper surface region; a shallow junction for each of the source and drain of the transistor underlying said upper surface of the silicon substrate; a metal silicide layer having a lower surface disposed adjacent the shallow junction of each of the source and drain in the silicon substrate and above said upper surface of the silicon substrate; and an epitaxial silicon layer disposed between said upper silicon surface and said lower surface of metal silicide and adjacent the shallow junction of each of the source and drain whereby the metal silicide does not extend below the upper silicon surface and encroach upon the shallow junction of each of the source and the drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In an integrated circuit in and on a silicon substrate having an active region including a bipolar transistor with an emitter, base and collector all of which a conductive contact is made comprising:
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a single crystalline silicon substrate with a upper surface region; a shallow junction for the emitter of the transistor underlying said upper surface of the silicon substrate; a metal silicide layer having a lower surface disposed adjacent the shallow junction of the emitter of the transistor in the silicon substrate and above said upper surface of the silicon substrate; and an epitaxial silicon layer disposed between said upper silicon surface and said lower surface of metal silicide and adjacent the shallow junction of the emitter whereby the metal silicide does not extend below the upper silicon surface and encroach upon the shallow junction of the emitter. - View Dependent Claims (11, 12, 13)
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Specification
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- Resources
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Current AssigneeLone Star Silicon Innovations LLC (Tanit Ventures Inc.)
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsOmid-Zohoor, Farrokh, Radjy, Nader
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Primary Examiner(s)Hardy, David B.
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Application NumberUS08/986,283Time in Patent Office689 DaysField of Search257/382, 257/383, 257/384, 257/754, 257/757, 257/769, 257/770, 438/607, 438/682, 438/683US Class Current257/383CPC Class CodesH01L 21/28052 the conductor comprising a ...H01L 21/28518 the conductive layers compr...H01L 21/28525 the conductive layers compr...H01L 29/41783 Raised source or drain elec...H01L 29/66272 Silicon vertical transistor...H01L 29/665 using self aligned silicida...H01L 29/66515 using self aligned selectiv...H01L 29/66575 where the source and drain ...
