Memories with programmable address decoding and systems and methods using the same
DCFirst Claim
Patent Images
1. A memory having address redirection circuitry comprising:
- an array of memory cells;
a hardwired address decoder for accessing a selected one of said cells in response to at least one address bit; and
a programmable volatile storage array for selectively redirecting said at least one address bit presented on an external bus to said address decoder in response to a control signal.
3 Assignments
Litigations
0 Petitions
Accused Products
Abstract
A memory 201 comprising an array 302 of memory cells, an address decoder 303, 305 for accessing a selected one of the cells in response to at least one address bit, and a programmable array 311 for selectively presenting the at least one address bit to the address decoder 303, 305 in response to a control signal.
34 Citations
28 Claims
-
1. A memory having address redirection circuitry comprising:
-
an array of memory cells; a hardwired address decoder for accessing a selected one of said cells in response to at least one address bit; and a programmable volatile storage array for selectively redirecting said at least one address bit presented on an external bus to said address decoder in response to a control signal. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A memory comprising:
-
at least one memory bank including an array of rows and columns of memory cells, a hardwired row decoder for selecting row of said array for access in response to at least one address bit and a hardwired column decoder for selecting a column of said array for access in response to at least one address bit; and a programmable volatile memory cell array for selectively redirecting an address bit presented on an external address bus to at least one of said row and column decoders in response to at least one decode control signal. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. Address decoding circuitry comprising:
-
a hardwired address decoder; and a programmable memory cell array for selectively redirecting addresses presented on an external address bus to said address decoder under control of a decode control signal. - View Dependent Claims (14, 15, 16, 17)
-
-
18. A memory system comprising:
-
an address bus; control circuitry; and a plurality of memory devices each comprising; an array of memory cells; a hardwired address decoder for decoding addresses for selectively accessing said cells in said array; a programmable array for selectively redirecting addresses transmitted on said bus to said decoder of said memory device in response to a control signal received from said control circuitry. - View Dependent Claims (19, 20, 21, 22, 23, 24)
-
-
25. A method of accessing data in a memory system including a plurality of memory devices each having an array of memory cells, a hardwired address decoder for decoding addresses for selectively accessing the cells in the array and a programmable array for selectively directing addresses to the decoder in response to a control signal, the method comprising the steps of:
-
presenting an address to the programmable array of each of the memory devices; presenting a control signal to the programmable array of a memory device to be accessed to direct the address to the decoder of the memory device to be accessed; and presenting a control signal to the programmable array of another memory device to disable the presentation of the address to the decoder of the another memory device. - View Dependent Claims (26, 27, 28)
-
Specification