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Memories with programmable address decoding and systems and methods using the same

DC
  • US 5,982,696 A
  • Filed: 06/06/1996
  • Issued: 11/09/1999
  • Est. Priority Date: 06/06/1996
  • Status: Expired due to Term
First Claim
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1. A memory having address redirection circuitry comprising:

  • an array of memory cells;

    a hardwired address decoder for accessing a selected one of said cells in response to at least one address bit; and

    a programmable volatile storage array for selectively redirecting said at least one address bit presented on an external bus to said address decoder in response to a control signal.

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