Hysteretic synchronization system for MPEG audio frame decoder

DC CAFC

US 5,982,830 A
Filed: 04/14/1997
Issued: 11/09/1999
Est. Priority Date: 01/20/1995
Status: Expired due to Term

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1. A system for synchronizing a data processing unit to a bitstream having synchronization codes successively spaced by a predetermined interval with data for processing disposed between the synchronization codes, said bitstream having a data header comprising a bitrate and a sampling frequency, said system comprising:

a detector for detecting said synchronization codes;

a sensor for sensing intervals between successive synchronization codes;

a comparator for comparing said intervals with said predetermined interval;

a controller for determining both;

(A) whether the system is synchronized to the bitstream after the comparator has detected a first predetermined number of said intervals; and

(B) whether the system is unsynchronized to the bitstream after the comparator has detected a second predetermined number of said intervals; and

a header sensor for sensing said data header and calculating said predetermined interval from said information.

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Abstract

An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected. The proper frame interval can be determined from the information in the header following each valid synchronization code, or can be determined by counting the number of bits between the first and second valid synchronization codes. The decoder can be muted while out of synchronization to minimize distortion of the audio presentation.

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29 Claims

1. A system for synchronizing a data processing unit to a bitstream having synchronization codes successively spaced by a predetermined interval with data for processing disposed between the synchronization codes, said bitstream having a data header comprising a bitrate and a sampling frequency, said system comprising:
- a detector for detecting said synchronization codes;
  
  a sensor for sensing intervals between successive synchronization codes;
  
  a comparator for comparing said intervals with said predetermined interval;
  
  a controller for determining both;
  
  (A) whether the system is synchronized to the bitstream after the comparator has detected a first predetermined number of said intervals; and
  
  (B) whether the system is unsynchronized to the bitstream after the comparator has detected a second predetermined number of said intervals; and
  
  a header sensor for sensing said data header and calculating said predetermined interval from said information.
- View Dependent Claims (2, 3, 4)
- - 2. A system according to claim 1, wherein the header sensor calculates said predetermined interval as a function of bitrate and sampling frequency.
  - 3. A system according to claim 1, wherein said first predetermined number of said intervals corresponds to successive synchronization codes equal to said predetermined interval;
    - wherein said second predetermined number of said intervals corresponds to successive synchronization codes that are not equal to said predetermined interval.
  - 4. A system according to claim 1, wherein said data header includes information from which said predetermined interval can be calculated.

5. A system for synchronizing a data processing unit to a bitstream having successively spaced synchronization codes and data disposed between the synchronization codes, the bitstream further comprising a data header following each synchronization code including information from which intervals between successive synchronization codes can be calculated, the system comprising:
- a detector for detecting said synchronization codes;
  
  a sensor for sensing intervals between successive synchronization codes;
  
  a comparator for comparing said intervals with synchronization code intervals;
  
  a controller for determining if the system is synchronized to the bitstream depending on satisfaction of a first predetermined condition and if the system is unsynchronized to the bitstream depending on satisfaction of a second predetermined condition; and
  
  a sensor for sensing said data header and calculating intervals between successive synchronization codes from said information.
- View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- - 6. A system as in claim 5, wherein said first predetermined condition comprises the comparator having detected a first predetermined number of said intervals and the second predetermined condition comprises the comparator having detected a second predetermined number of said intervals.
  - 7. A system as in claim 6, wherein said first predetermined number corresponds to successive synchronization codes equal to said predetermined interval and said second predetermined number corresponds to successive synchronization codes not equal to said predetermined interval.
  - 8. A system as in claim 6, wherein said first and second predetermined numbers are each greater than one.
  - 9. A system as in claim 6, wherein said first and second predetermined numbers are equal.
  - 10. A system as in claim 5, in which:
    - said data comprises frames of encoded audio data; and
      
      the processing unit comprises a decoder for decoding said frames.
  - 11. A system as in claim 10, wherein the controller further inhibits the decoder from outputting frames of decoded data while the system is unsynchronized to said bitstream.
  - 12. A system as in claim 10, wherein the controller further inhibits the decoder from decoding said frames based on a third predetermined condition.
  - 13. A system according to claim 12, wherein the third predetermined condition comprises the system being unsynchronized to said bitstream.
  - 14. A system as in claim 5, wherein the header sensor senses and detects header syntax and the controller determines that the system is synchronized to the bitstream if the header sensor detects that said header syntax following a first one of said successive synchronization codes is normal.
  - 15. A system as in claim 5, wherein:
    - said bitstream comprises bits of data such that said intervals between successive synchronization codes corresponds to a number of said bits; and
      
      the system further comprises a counter for counting said bits between successive synchronization codes to determine said number of said bits and said interval between successive synchronization codes.

16. A method for synchronizing a data processing system to a bitstream including synchronization codes successively spaced from each other by a predetermined interval, data disposed between the synchronization codes, and a data header including information from which said predetermined interval can be calculated, comprising the steps of:
- (a) detecting said synchronization codes;
  
  (b) sensing intervals between successive synchronization codes;
  
  (c) comparing said intervals with said predetermined interval;
  
  (d) determining that the system is synchronized to the bitstream based on a first predetermined condition;
  
  (e) determining that the system is unsynchronized to the bitstream based on a second predetermined condition; and
  
  (f) sensing said data header and calculating said predetermined interval from said information between steps (a) and (c).
- View Dependent Claims (17, 18, 19)
- - 17. A method as in claim 16, wherein:
    - said information comprises a bitrate and a sampling frequency; and
      
      step (f) comprises calculating said interval as a predetermined function of the bitrate and the sampling frequency.
  - 18. A method as in claim 17, wherein the predetermined function is N=K(bitrate/sampling frequency), where N is said predetermined interval and K is a predetermined constant.
  - 19. A method as in claim 16, wherein said first predetermined condition is:
    - after a first predetermined number of said intervals corresponding to successive synchronization codes equal to said predetermined interval have been detected; and
      
      said second predetermined condition is;
      
      after a second predetermined number of said intervals corresponding to successive synchronization codes that are not equal to said predetermined interval have been detected.

20. A method for synchronizing a data processing system to a bitstream including synchronization codes spaced at a predetermined interval, data disposed between the synchronization codes, and a data header including information from which said predetermined interval can be calculated, comprising the steps of:
- (a) detecting said synchronization codes;
  
  (b) sensing intervals between successive synchronization codes;
  
  (c) comparing said intervals with said predetermined interval;
  
  (d) determining system synchronization and unsynchronization based on predetermined conditions, wherein;
  
  (e) sensing said header and calculating said predetermined interval from said information between steps (a) and (c).
- View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29)
- - 21. A method as in claim 20, wherein said predetermined conditions comprise:
    - the system is synchronized to the bitstream after a first predetermined number of said intervals corresponding to successive synchronization codes that are equal to said predetermined interval have been detected; and
      
      the system is unsynchronized to the bitstream after a second predetermined number of said intervals corresponding to successive synchronization codes that are not equal to said predetermined interval have been detected.
  - 22. A method as in claim 21, wherein said first and second predetermined numbers are each larger than one.
  - 23. A method as in claim 21, wherein said first and second predetermined numbers are equal.
  - 24. A method as in claim 20, wherein:
    - said data comprises frames of encoded audio data;
      
      the system comprises a decoder for decoding said frames; and
      
      step (d) further comprises synchronizing the decoder to said frames.
  - 25. A method as in claim 20, wherein step (d) further comprises inhibiting the decoder from outputting frames of decoded data while the system is unsynchronized to said bitstream.
  - 26. A method as in claim 20, wherein step (e) further comprises inhibiting decoding said frames while the system is unsynchronized to said bitstream.
  - 27. A method as in claim 20, wherein:
    - the method further comprises the step, performed prior to step (c), of;
      
      (f) sensing and detecting header syntax following a first one of said successive synchronization codes.
  - 28. A method as in claim 27, wherein step (d) further comprises determining that the system is synchronized to the bitstream only if said syntax of said header following said first one of said successive synchronization codes is normal.
  - 29. A method as in claim 20, wherein:
    - said bitstream comprises bits of data such that said predetermined interval corresponds to a number of said bits; and
      
      the method further comprises the step, performed prior to step (c), of;
      
      (f) counting said bits between successive synchronization codes to determine said number of said bits and said corresponding predetermined interval.

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Current Assignee
Avago Technologies General IP PTE Limited (Broadcom, Inc.)
Original Assignee
LSI Logic Corporation (Broadcom, Inc.)
Inventors
Maturi, Greg, Dierke, Gregg
Primary Examiner(s)
Pham, Chi H.
Assistant Examiner(s)
WEBSTER, BRYAN E

Application Number

US08/843,222
Time in Patent Office

939 Days
Field of Search

375/354, 375/355, 375/359, 375/360, 375/364, 375/365, 375/366, 375/368, 381/94, 327/141, 327/162, 348/512, 348/513, 348/516, 348/518, 348/517, 348/390, 348/497, 348/500, 370/503, 370/506, 370/509, 370/514
US Class Current

375/366
CPC Class Codes

G10L 19/02   using spectral analysis, e....

H04J 3/0608   Detectors therefor, e.g. co...

H04L 7/08   the synchronisation signals...

H04N 21/2368   Multiplexing of audio and v...

H04N 21/4305   Synchronising client clock ...

H04N 21/4341   Demultiplexing of audio and...

H04N 21/439   Processing of audio element...

Hysteretic synchronization system for MPEG audio frame decoder

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Abstract

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29 Claims

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Hysteretic synchronization system for MPEG audio frame decoder

First Claim

3 Assignments

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Abstract

45 Citations

29 Claims

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