Method and apparatus for a self-timed and self-enabled distributed clock

US 5,987,620 A
Filed: 11/14/1997
Issued: 11/16/1999
Est. Priority Date: 09/19/1997
Status: Expired due to Term

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1. A self-timed and self-enabled clock circuit for synchronizing operation of a digital circuit, comprising:

a control circuit that detects input clock pulses and that provides an enable signal while the input clock pulses are provided; and

a clock delay device, coupled to the control circuit, that has a plurality of inputs and an output that provides an output clock pulse when the clock delay device is enabled, the inputs including;

a feedback clock input that is coupled to the output of the clock delay device;

a clock input for receiving the input clock pulses; and

an enable input that receives the enable signal to enable the clock delay device;

wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses.

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Abstract

A self-timed and self-enabled distributed clock is provided for pipeline processor design having functional blocks which include one or more pipeline stages for processing instructions and operations. Each pipeline stage of the processor includes self-timed logic and an enable signal to set up the valid data input to the next pipeline stage. The self-timed logic is used instead of a central, synchronous clock having a predetermined period and provides flexibility of expanding or contracting the clock period in multiple time units depending on the functionality of each pipeline stage. The interfacing between the pipeline stages is handled by a queue buffer which stores incoming instructions to keep the pipeline fully occupied any time there are instructions in the pipeline. A functional unit and its distributed clock are activated only if there is instruction in the pipeline and is otherwise idle. The self-timed clock provides a fixed time unit or plurality of time units to each pipeline stage which is deterministic for verification and testing purposes. The self-timed and self-enabled clock, along with the queue buffers associated therewith, provide flexibility for implementing each pipeline stage while reducing power, noise and clock skew and while improving the overall instruction-per-cycle performance of the processor.

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58 Claims

1. A self-timed and self-enabled clock circuit for synchronizing operation of a digital circuit, comprising:
- a control circuit that detects input clock pulses and that provides an enable signal while the input clock pulses are provided; and
  
  a clock delay device, coupled to the control circuit, that has a plurality of inputs and an output that provides an output clock pulse when the clock delay device is enabled, the inputs including;
  
  a feedback clock input that is coupled to the output of the clock delay device;
  
  a clock input for receiving the input clock pulses; and
  
  an enable input that receives the enable signal to enable the clock delay device;
  
  wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- - 2. The clock circuit of claim 1 wherein the clock delay device comprises a plurality of delay blocks sequentially coupled together.
  - 3. The clock circuit of claim 2 wherein the output of the clock delay device is coupled to each of the plurality of delay blocks such that each output clock pulse resets each of the plurality of delay blocks.
  - 4. The clock circuit of claim 2 wherein at least one of the plurality of delay blocks provides an intermediate clock edge.
  - 5. The clock circuit of claim 4 wherein the intermediate clock edge is used to control an associated functional block.
  - 6. The clock circuit of claim 2 wherein each of the delay blocks comprises coupled logic gates.
  - 7. The clock circuit of claim 2 wherein one of the plurality of delay blocks comprises programmable delay logic.
  - 8. The clock circuit of claim 7 wherein the programmable delay logic comprises:
    - a plurality of delay devices; and
      
      selection logic coupled to select any one of the plurality of delay devices.
  - 9. The clock circuit of claim 8 further comprising:
    - each of the plurality of delay devices receiving an external clock signal and providing a corresponding clock edge; and
      
      the selection logic selecting a delay device providing a clock edge that most closely corresponds with the external clock signal.
  - 10. The clock circuit of claim 9 wherein the selection logic selects a delay device having a clock edge that occurs closest to a controlling edge of the external clock signal.
  - 11. The clock circuit of claim 1 wherein the input clock pulses are provided from an output of another self-timed and self-enabled clock circuit.
  - 12. The clock circuit of claim 1 further comprising:
    - the clock delay device including a second clock input; and
      
      wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses and clock signals provided to the second clock input.
  - 13. The clock circuit of claim 12 further comprising:
    - the input clock pulses being provided from an output of a previous self-timed and self-enabled clock circuit; and
      
      the second clock input receiving clock pulses provided from a subsequent self-timed and self-enabled clock circuit.
  - 14. The clock circuit of claim 1 further comprising:
    - a pulse shaper circuit, coupled to the clock delay device, that provides the output clock pulses.
  - 15. The clock circuit of claim 1 further comprising:
    - the control circuit further including a stall input, the control circuit disabling the clock delay device if a stall signal is received at the stall input.

16. A distributed clock system for a digital circuit, comprising:
- a first self clock that provides first output clock pulses when enabled, the first self clock comprising;
  
  an output, a first input coupled to the output and a second input;
  
  wherein the first self clock is enabled by each clock pulse received at the second input and synchronizes the first output clock pulses with respective clock signals received at the second input; and
  
  a second self clock that provides second output clock pulses when enabled, the second self clock comprising;
  
  an output, a first input coupled to the output of the second self clock, and a second input coupled to the output of the first self clock;
  
  wherein the second self clock is enabled by each clock pulse received at the second input and synchronizes the second output clock pulse with respective clock signals received at the second input of the second self clock.
- View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
- - 17. The distributed clock system of claim 16 wherein the second input of the first self clock receives output clock pulses from a third self clock.
  - 18. The distributed clock system of claim 16 wherein the second input of the first self clock receives an external clock signal.
  - 19. The distributed clock system of claim 16 further comprising:
    - the second clock having a third input that receives an external clock signal; and
      
      wherein the second self clock synchronizes the second output clock pulses with respective clock signals received at its second and third inputs.
  - 20. The distributed clock system of claim 16 further comprising:
    - the second self clock having a third input that receives output clock pulses from a third self clock; and
      
      wherein the second self clock synchronizes the second output clock pulses with respective clock signals received at its second and third inputs.
  - 21. The distributed clock system of claim 16 wherein the first and second self clocks operate at approximately the same frequency.
  - 22. The distributed clock system of claim 16 wherein at least one of the first and second self clocks operates at a frequency that is a multiple of other of the first and second self clocks.
  - 23. The distributed clock system of claim 16 wherein the first and second self clocks operate asynchronously relative to each other.
  - 24. The distributed clock system of claim 16 further comprising:
    - a first functional block receiving the first output pulses from the first self clock; and
      
      a second functional block receiving the second output pulses from the second self clock.
  - 25. The distributed clock system of claim 24 wherein the first and second functional blocks operate at approximately the same frequency.
  - 26. The distributed clock system of claim 24 wherein the first and second functional blocks operate asynchronously with respect to each other.
  - 27. The distributed clock system of claim 24 further comprising:
    - a first queue buffer, coupled to the first functional block and receiving the first clock pulses, that receives data for the first functional block; and
      
      a second queue buffer, coupled to the second functional block and receiving the second clock pulses, that receives data from the first functional block for the second functional block.
  - 28. The distributed clock system of claim 16 further comprising:
    - a functional block receiving the second output pulses from the second self clock; and
      
      a queue buffer, coupled to the functional block and receiving the second clock pulses, that receives data for the functional block.
  - 29. The distributed clock system of claim 28 further comprising:
    - the second self clock having an enable input and providing the second output pulses if an enable signal is provided to the enable input; and
      
      a control block, coupled to the functional block, the queue buffer and the output of the first self clock, that provides the enable signal while receiving clock pulses from the first self clock.
  - 30. The distributed clock system of claim 29 further comprising:
    - the functional block detecting a stall condition and asserting a stall signal; and
      
      the control block receiving the stall signal and providing the enable signal only while the stall signal is not asserted.
  - 31. The distributed clock system of claim 30 further comprising:
    - a second functional block that detects a full condition and that asserts a full signal; and
      
      the control block receiving the full signal and providing the enable signal only while the full signal is not asserted.
  - 32. The distributed clock system of claim 29 further comprising:
    - the control block detecting a full condition of the queue buffer and asserting a full signal to a previous functional block.

33. A processor, comprising:
- a plurality of functional blocks, each comprising;
  
  a queue buffer having a data input and a data output, the data input being the data input of the respective functional block;
  
  an execution unit that has an input coupled to the data output of the queue buffer and an execution data output, the execution output being the data output of the respective functional block;
  
  a self clock that has an output, a first clock input, a feedback input coupled to the output of the self clock, and an enable input;
  
  the self clock, when enabled, providing output clock pulses that are synchronized with clock pulses received at the first clock input; and
  
  a control block, coupled to the queue buffer, the execution unit and self clock, that has an enable output coupled to the enable input of the self clock;
  
  the control block enabling the self clock while the execution unit is processing data and while clock pulses are received at the first clock input of the self clock; and
  
  the plurality of functional blocks including a first and second functional blocks coupled together;
  
  wherein a first clock input of the second functional block is coupled to a clock output of the first functional block, and wherein the data output of the first functional block is coupled to the data input of the second functional block.
- View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
- - 34. The processor of claim 33 wherein the processor comprises a pipeline processor, and wherein each of the plurality of functional blocks is associated with a stage of the pipeline processor.
  - 35. The processor of claim 33 wherein at least one functional block further comprises:
    - a second queue buffer coupled to the execution unit; and
      
      a second self clock coupled to the control block and to the second queue buffer.
  - 36. The processor of claim 33 wherein the queue buffer comprises a plurality of storage devices.
  - 37. The processor of claim 36 wherein the plurality of storage devices comprise registers.
  - 38. The processor of claim 33 further comprising:
    - the first functional block having a self clock with a second clock input; and
      
      wherein a clock output of the second functional block is coupled to the second clock input of the first functional block.
  - 39. The processor of claim 33 wherein at least one of the plurality of functional blocks receives an external clock signal.
  - 40. The processor of claim 33 further comprising:
    - the execution unit detecting a stall condition and asserting a stall signal; and
      
      the control block receiving the stall signal and disabling the self clock from providing clock pulses while the stall signal is provided.
  - 41. The processor of claim 33 wherein the control unit includes a full input and disables the self clock from providing clock pulses while a full signal is received at the full input.
  - 42. The processor of claim 41, the control unit including a full output, wherein the control unit detects a full condition of the queue buffer and asserts a full signal indicative thereof via the full output.
  - 43. The processor of claim 42 further comprising:
    - a full output of the second functional block coupled to a full input of the first functional block.
  - 44. The processor of claim 33 further comprising:
    - the queue buffer including a first storage device coupled to a second storage device and to the execution unit;
      
      the second storage device storing new data from a previous functional block during a stall condition; and
      
      the first storage device storing current data during the stall condition.
  - 45. The processor of claim 33 further comprising:
    - the queue buffer including a first storage device coupled to a second storage device and to the execution unit;
      
      the control block enabling the self clock to provide clock pulses only if valid data is stored in both the first and second storage devices.

46. A method of operating each of a plurality of coupled functional blocks of a digital system, comprising:
- receiving input data and corresponding first input clock pulses;
  
  activating a self clock to provide an output clock pulse for each first input clock pulse;
  
  processing the input data and generating output data;
  
  generating, by the self clock, an output clock pulse to correspond with each output data; and
  
  deactivating the self clock while first input clock pulses are not received or during a stall condition.
- View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
- - 47. The method of claim 46 further comprising:
    - receiving, from a subsequent functional block, second input clock pulses; and
      
      synchronizing, by the self clock while enabled, output clock pulses with the first and second input clock pulses.
  - 48. The method of claim 46, the first input clock pulses being provided from a previous functional block, further comprising:
    - receiving, from a subsequent functional block, second input clock pulses; and
      
      operating the previous, a current and the subsequent functional blocks asynchronously with respect to each other.
  - 49. The method of claim 46, the first input clock pulses being provided from a previous functional block, further comprising:
    - receiving, from a subsequent functional block, second input clock pulses; and
      
      operating at least one of the previous, a current and the subsequent functional blocks at a frequency that is a multiple of at least one other of the previous, current and subsequent functional blocks.
  - 50. The method of claim 46 further comprising:
    - the receiving first input clock pulses comprising receiving an external clock signal.
  - 51. The method of claim 46 further comprisinggenerating, by the self clock, an intermediate clock edge between each of the first input clock pulses and the corresponding output clock pulses.
  - 52. The method of claim 46 further comprising:
    - determining a stall condition; and
      
      disabling the self clock from providing output clock pulses during the stall condition.
  - 53. The method of claim 52 further comprising:
    - refreshing current data in a current functional block during the stall condition.
  - 54. The method of claim 46 further comprising:
    - receiving a full signal from a subsequent functional block; and
      
      disabling the self clock while the full signal is asserted.
  - 55. The method of claim 54 further comprising:
    - refreshing current data in a current functional block while the full signal is asserted.
  - 56. The method of claim 52 further comprising:
    - queuing the input data in a queue buffer;
      
      detecting a full condition of the queue buffer; and
      
      disabling the self clock during the full condition.
  - 57. The method of claim 56 further comprising:
    - refreshing current data in a current functional block during the full condition.
  - 58. The method of claim 56, further comprising:
    - generating a full signal indicative of the full condition; and
      
      providing the full signal to a previous functional block.

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Current Assignee
Janus Semiconductor Research, LLC
Original Assignee
Thang V. Tran
Inventors
Tran, Thang
Primary Examiner(s)
Palys, Joseph E.
Assistant Examiner(s)
Hossain, Abu

Application Number

US08/969,866
Time in Patent Office

732 Days
Field of Search

395/559, 395/555, 395/551, 395/568, 395/575, 713/500, 713/501, 713/503, 713/400, 713/401
US Class Current

713/600
CPC Class Codes

G06F 1/10   Distribution of clock signa...

G06F 9/3836   Instruction issuing, e.g. d...

G06F 9/3867   using instruction pipelines

G06F 9/3871   Asynchronous instruction pi...

Method and apparatus for a self-timed and self-enabled distributed clock

First Claim

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Abstract

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58 Claims

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Method and apparatus for a self-timed and self-enabled distributed clock

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Abstract

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58 Claims

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