Data communication for memory
DC
First Claim
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1. An integrated circuit memory comprising:
- memory cells for storing data;
data read circuitry for reading and outputting data stored in the memory cells on an external data communication line; and
an output signal circuit for providing a signal on an external connection indicating that data is available on the external data communication line wherein the output signal circuit comprises a trigger circuit for initiating the signal on the external connection, and the trigger circuit initiates the signal on the external connection in response to an externally provided address signal.
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Abstract
A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.
93 Citations
30 Claims
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1. An integrated circuit memory comprising:
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memory cells for storing data; data read circuitry for reading and outputting data stored in the memory cells on an external data communication line; and an output signal circuit for providing a signal on an external connection indicating that data is available on the external data communication line wherein the output signal circuit comprises a trigger circuit for initiating the signal on the external connection, and the trigger circuit initiates the signal on the external connection in response to an externally provided address signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated memory circuit comprising:
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randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines; and a trigger circuit which produces a signal coupled to an external connection indicating that data is available on the plurality of output data lines, wherein the trigger circuit is responsive to an address strobe signal during a read operation. - View Dependent Claims (13, 14)
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15. An integrated memory circuit comprising:
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randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines; and a trigger circuit which produces a signal coupled to an external connection indicating that data is available on the plurality of output data lines, wherein the trigger circuit is responsive to a column address strobe signal and an output enable signal.
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16. A data processing system comprising:
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a microprocessor; and a memory device coupled to the microprocessor, the memory device comprising; memory cells for storing data, data read circuitry for reading and outputting data stored in the memory cells on an external data communication line coupled to the microprocessor, and an output signal circuit for providing a data strobe signal on an external connection coupled to the microprocessor indicating that data is available on the external data communication line, whereby the microprocessor monitors the data strobe signal and retrieves data from the external data communication line in response to the output data strobe signal, wherein the data strobe signal is coupled to the external data communication line through a push/pull driver circuit. - View Dependent Claims (17, 18, 19, 20)
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21. A data processing system comprising:
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a microprocessor; and a memory device coupled to the microprocessor, the memory device comprising; memory cells for storing data, data read circuitry for reading and outputting data stored in the memory cells on an external data communication line coupled to the microprocessor, and an output signal circuit for providing a data strobe signal on an external connection coupled to the microprocessor indicating that data is available on the external data communication line, whereby the microprocessor monitors the data strobe signal and retrieves data from the external data communication line in response to the output data strobe signal, wherein the data strobe signal is coupled to the external data communication line through a pull-up driver circuit.
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22. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; generating an output data signal on an external connection to indicate that data is coupled to the output communication lines; receiving the output data signal with a microprocessor; and latching the data coupled to the output communication lines. - View Dependent Claims (23, 24)
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25. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; and generating an output data signal on an external connection to indicate that data is coupled to the output communication lines, wherein the output data signal toggles logic states when new data is available on the output communication lines.
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26. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; and generating an output data signal on an external connection to indicate that data is coupled to the output communication lines, wherein generating an output data signal comprises; receiving an address strobe signal; generating a delayed pulse signal from the address strobe signal; pulsing the output data signal low during a read operation in response to the delayed pulse signal; and coupling the output data signal to the external connection.
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27. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; and generating an output data signal on an external connection to indicate that data is coupled to the output communication lines, wherein generating an output data signal comprises; receiving an address strobe signal; generating a delayed pulse signal from the address strobe signal; receiving a clock signal; pulsing the output data signal to an active state during a read operation in response to the delayed pulse signal and the clock signal; and coupling the output data signal to the external connection.
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28. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; and generating an output data signal on an external connection to indicate that data is coupled to the output communication lines, wherein generating an output data signal comprises; receiving an address strobe signal; toggling the output data signal to an opposite logic state during a read operation in response to the address strobe signal; and coupling the output data signal to the external connection.
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29. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; and generating an output data signal on an external connection to indicate that data is coupled to the output communication lines, wherein generating an output data signal comprises; receiving an address strobe signal; receiving a clock signal; toggling the output data signal to an opposite logic state during a read operation in response to the address strobe signal and the clock signal; and coupling the output data signal to the external connection.
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30. A method of reading a memory circuit, the method comprising:
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receiving an external signal requesting data output from the memory circuit; coupling data stored in the memory circuit to output communication lines; and generating an output data signal on an external connection to indicate that data is coupled to the output communication lines, wherein generating an output data signal comprises; comparing a voltage level of an output communication line with a predetermined voltage level; generating an internal signal if a voltage on the output communication line is greater than the predetermined voltage level; and generating the output data signal in response to the internal signal.
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Specification
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Litigation Data
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Current AssigneeRound Rock Research LLC
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Original AssigneeMicron Technology, Inc.
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InventorsManning, Troy A., Cloud, Eugene H., Williams, Brett
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Primary Examiner(s)Nguyen, Tan T.
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Application NumberUS08/966,762Time in Patent Office764 DaysField of Search365/189.01, 365/189.05, 365/189.08, 365/233.5, 365/233US Class Current365/189.15CPC Class CodesG11C 11/4076 Timing circuits for regener...G11C 7/1051 Data output circuits, e.g. ...G11C 7/1063 Control signal output circu...G11C 7/22 Read-write [R-W] timing or ...
