Methods and arrangements for improved spacer formation within a semiconductor device
DC CAFC
First Claim
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1. A method for forming substantially uniformly sized spacers on transistor gate arrangements within semiconductor devices on a common substrate, the method comprising:
- forming a plurality of gate arrangements on a top surface of the substrate, wherein two of the plurality of gate arrangements are positioned parallel to one another and separated by a defined space;
forming a dielectric layer over at least a portion of the two gate arrangements and at least a portion of the defined space;
removing portions of the dielectric layer to form a plurality of spacers, wherein each of the plurality of spacers physically contacts one of the two gate arrangements and the substrate, and wherein the spacers located within the defined space each have a base width that is approximately the same;
configuring one of the two gate arrangements to control an electrical current between a source region and a drain region formed in the substrate; and
configuring the remaining one of the two transistor gate arrangements to be non-operational.
2 Assignments
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3 Petitions
Accused Products
Abstract
Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
16 Citations
15 Claims
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1. A method for forming substantially uniformly sized spacers on transistor gate arrangements within semiconductor devices on a common substrate, the method comprising:
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forming a plurality of gate arrangements on a top surface of the substrate, wherein two of the plurality of gate arrangements are positioned parallel to one another and separated by a defined space; forming a dielectric layer over at least a portion of the two gate arrangements and at least a portion of the defined space; removing portions of the dielectric layer to form a plurality of spacers, wherein each of the plurality of spacers physically contacts one of the two gate arrangements and the substrate, and wherein the spacers located within the defined space each have a base width that is approximately the same; configuring one of the two gate arrangements to control an electrical current between a source region and a drain region formed in the substrate; and configuring the remaining one of the two transistor gate arrangements to be non-operational. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for controlling the width of a spacer in a transistor arrangement in a semiconductor device, the method comprising:
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forming an operational transistor gate arrangement on a substrate at a first position and a non-operational transistor gate arrangement at a second position on the substrate, such that the operational and non-operational transistor gate arrangements are separated and adjacent to each other with a space therebetween; forming a dielectric layer over at least a portion of the operational and non-operational transistor gate arrangements and within the space; removing portions of the dielectric layer to form a first spacer that physically contacts a sidewall of the operational transistor gate arrangement and the substrate and extends into the space, and a second spacer that physically contacts a sidewall of the non-operational transistor gate arrangement and the substrate and extends into the space, and wherein each of the first and second spacers extends into the space substantially the same distance. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for controlling the formation of spacers on a plurality of polysilicon lines in a semiconductor device arrangement, the method comprising:
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forming a plurality of polysilicon lines on a top surface of a substrate; forming at least one dummy polysilicon line on the substrate, the dummy polysilicon line being substantially parallel to at least a portion of one of the polysilicon lines and separated from the portion of the one of the polysilicon lines by a defined space that has a critical dimension; covering the polysilicon lines, the at least one dummy polysilicon line and the top surface of the substrate below the defined space, with at least one dielectric layer; and removing portions of the at least one dielectric layer to form a plurality of separate dielectric spacers each of which contacts a sidewall of one of the plurality of polysilicon lines and the substrate, and plurality of separate dummy dielectric spacers that are connected to the at least one dummy polysilicon line and the substrate.
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Specification
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Litigation Data
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Current AssigneeLone Star Silicon Innovations LLC (Tanit Ventures Inc.)
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsEn, William G., Ngo, Minh Van, Yang, Chih-Yuh, Foote, David K., Bell, Scott A., Karlsson, Olov B., Lyons, Christopher F.
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Primary Examiner(s)Utech, Benjamin L.
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Assistant Examiner(s)UMEZ ERONINI, LYNETTE T
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Application NumberUS08/993,830Time in Patent Office971 DaysField of Search438/706, 438/719, 438/696, 438/695, 438/639, 438/595, 438/FOR 199US Class Current438/595CPC Class CodesH01L 21/31116 by dry-etching
