Semiconductor memory device with improved flexible redundancy scheme
DC
First Claim
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1. A semiconductor memory device, comprising:
- a plurality of first memory blocks each having a plurality of first normal memory cells arranged in a matrix of rows and columns, each of said plurality of first memory blocks including word lines provided corresponding to said rows, respectively, and the first memory blocks aligned in the column direction; and
a plurality of first spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks, each row of said plurality of first spare memory cells being capable of replacing a defective row including a defective first normal memory cell in said plurality of first memory blocks.
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Abstract
A spare memory array having spare memory cells common to a plurality of normal sub-arrays having a plurality of normal memory cells is provided. A spare line in the spare array can replace a defective line in the plurality of normal sub-array. The defective line is efficiently repaired by replacement in an array divided into blocks or sub-arrays.
55 Citations
7 Claims
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1. A semiconductor memory device, comprising:
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a plurality of first memory blocks each having a plurality of first normal memory cells arranged in a matrix of rows and columns, each of said plurality of first memory blocks including word lines provided corresponding to said rows, respectively, and the first memory blocks aligned in the column direction; and
a plurality of first spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks, each row of said plurality of first spare memory cells being capable of replacing a defective row including a defective first normal memory cell in said plurality of first memory blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7)
a plurality of second memory blocks arranged alternatively with said plurality of first memory blocks along the column direction, the second memory blocks each having a plurality of second normal memory cells arranged in a matrix of rows and columns; and
a plurality of second spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of second memory blocks, each row of said plurality of second spare memory cells being capable of replacing a defective row including a defective second normal memory cell in said plurality of second memory blocks.
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3. The semiconductor memory device as recited in claim 2, further comprising a plurality of sense amplifier bands provided between each of said plurality of first memory blocks and each of said second memory blocks, and shared by adjacent memory blocks in the column direction for sensing and amplifying data in each column of the adjacent memory block including a selected memory cell when activated.
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4. The semiconductor memory device as recited in claim 2, wherein the first memory blocks and the second memory blocks share a circuit related to a memory cell selection operation.
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5. The semiconductor memory device as recited in claim 3, wherein
said plurality of first memory blocks, said plurality of second memory blocks and said plurality of sense amplifier bands form a first memory array, and said semiconductor memory device further comprises: -
a second memory array having a same arrangement as the first memory array; and
control circuitry for driving one memory block from the first and second memory arrays into a selected state in a normal operation mode, and for simultaneously driving a prescribed number of memory blocks from each of said first and second memory arrays into a selected state in a particular operation mode.
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6. The semiconductor memory device as recited in claim 1, wherein the first normal memory cells and the first spare memory cells are arranged alignedly in the column direction.
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7. The semiconductor memory device as recited in claim 1, wherein the first memory blocks other than said particular one has no first spare memory cells.
Specification
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Litigation Data
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Current AssigneeLimestone Memory Systems LLC (Acacia Research Corporation)
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Original AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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InventorsHidaka, Hideto
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Primary Examiner(s)Tran, Andrew Q.
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Application NumberUS09/251,352Time in Patent Office818 DaysField of Search365/200, 365/230.03, 365/190, 365/208, 365/225.7US Class Current365/200CPC Class CodesG11C 29/783 with refresh of replacement...G11C 29/808 using a flexible replacemen...
