Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media
DC
First Claim
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1. A circuit comprising:
- a first circuit comprising a packer circuit and an encoder/serializer circuit, wherein said first circuit is configured to receive a first series of data packets having a first bit-width and present a second series of data packets having a second bit-width in response to said first series of data packets; and
a second circuit comprising a decoder/deserializer circuit and an unpacker circuit, wherein said second circuit is configured to present a third series of data packets having said first bit-width in response to said second series of data packets.
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Abstract
An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.
41 Citations
15 Claims
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1. A circuit comprising:
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a first circuit comprising a packer circuit and an encoder/serializer circuit, wherein said first circuit is configured to receive a first series of data packets having a first bit-width and present a second series of data packets having a second bit-width in response to said first series of data packets; and
a second circuit comprising a decoder/deserializer circuit and an unpacker circuit, wherein said second circuit is configured to present a third series of data packets having said first bit-width in response to said second series of data packets. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
a buffer circuit configured to hold one or more of said first series of data packets.
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3. The circuit according to claim 1, wherein said second circuit comprises:
a buffer circuit configured to hold one or more of said third series of data packets.
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4. The circuit according to claim 1, wherein said second series of data packets are presented on a serial link.
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5. The circuit according to claim 4, wherein said serial link comprises a fiber channel serial link.
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6. The circuit according to claim 5, wherein said encoder/serializer circuit and said decoder/deserializer circuit comprise 8b10b compliant devices.
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7. The circuit according to claim 1, wherein said packer circuit comprises:
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a first register configured to receive data packets having said first bit-width from said buffer circuit and present data packets having said first bit-width to a second register and a finite state machine in response to a clock signal;
said second register configured to present data packets having said first bit-width to said finite state machine in response to said clock signal; and
said finite state machine configured to present data packets having said second bit-width.
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8. The circuit according to claim 1, wherein said unpacker circuit comprises:
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a first register configured to receive data packets having said second bit-width and present data packets having said second bit-width to a second register and a finite state machine in response to a clock signal;
said second register configured to present data packets having said second bit-width to said finite state machine in response to said clock signal; and
said finite state machine configured to present data packets having said first bit-width to said buffer circuit.
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9. A circuit comprising:
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means for receiving a first series of data packets having a first bit-width and presenting a second series of data packets having a second bit-width in response to said first series of data packets, said receiving means comprising a packer circuit and an encoder/serializer circuit; and
means for presenting a third series of data packets having said first bit-width in response to said second series of data packets, said presenting means comprising a decoder/deserializer circuit and an unpacker circuit.
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10. A method for transmitting data having a first bit-width over media having a second bit-width comprising the steps of:
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(a) receiving a first series of data packets having said first bit-width, generating a second series of data packets having said second bit-width in response to said first series of data packets, and packing, encoding/serializing, and presenting said second series of data packets to said media; and
(b) receiving, decoding/deserializing, and unpacking said second series of data packets, and generating a third series of data packets having said first bit-width in response to said second series of data packets. - View Dependent Claims (11, 12, 13, 14, 15)
(a-1) buffering one or more of said first series of data packets; and
(a-2) generating said second series of data packets in response to said buffered data packets.
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12. The method according to claim 10, wherein step (b) comprises the steps of:
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(b-1) generating said third series of data packets; and
(b-2) buffering one or more of said third series of data packets.
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13. The method according to claim 10, wherein said second series of data packets are presented on a serial link.
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14. The method according to claim 13, wherein said serial link comprises a fiber channel serial link.
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15. The method according to claim 13, wherein said encoding/serializing and decoding/deserializing steps are 8b10b compliant.
Specification
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Litigation Data
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Current AssigneeNbit Communications Systems, LLC (Equitable IP Corporation)
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsMatthews, Joe P.
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Primary Examiner(s)Lee, Thomas
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Assistant Examiner(s)SCHUSTER, KATHARINA W
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Application NumberUS09/182,561Time in Patent Office1,097 DaysField of Search710/66, 710/127, 710/62, 710/65, 710/126, 712/225, 717/5, 708/551, 370/471, 375/220US Class Current710/66CPC Class CodesG06F 5/00 Methods or arrangements for...H04Q 11/04 for time-division multiplex...H04Q 2213/13034 A/D conversion, code compre...H04Q 2213/13103 MemoryH04Q 2213/13174 Data transmission, file tra...H04Q 2213/13296 Packet switching, X.25, fra...H04Q 2213/1332 Logic circuits
