Interface for low-voltage semiconductor devices
DCFirst Claim
Patent Images
1. An integrated circuit comprising:
- a output driver coupled between a first noisy supply at a first voltage level and a pin;
a voltage down converter coupled between a first quiet supply at the first voltage level and a first node at a second voltage level, wherein the second voltage level is lower than the first voltage level;
a core circuit coupled to the first node, wherein the core circuit comprises programmable logic; and
a level shifting predriver, coupled between a control electrode of the output driver and the core circuit, wherein the predriver generates a voltage high output at the first voltage level and the core circuit generates a voltage high output at a second voltage level.
0 Assignments
Litigations
0 Petitions
Accused Products
Abstract
A technique and circuitry to interface an integrated circuit to other integrated circuits in a mixed-voltage mode environment. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage level. The input and output signals to and from the integrated circuit will be compatible with the external supply level. Specifically, a level shifter (1317) or similar conversion circuit is used to convert voltages compatible with the internal supply level to be compatible with the external supply level.
140 Citations
35 Claims
-
1. An integrated circuit comprising:
-
a output driver coupled between a first noisy supply at a first voltage level and a pin;
a voltage down converter coupled between a first quiet supply at the first voltage level and a first node at a second voltage level, wherein the second voltage level is lower than the first voltage level;
a core circuit coupled to the first node, wherein the core circuit comprises programmable logic; and
a level shifting predriver, coupled between a control electrode of the output driver and the core circuit, wherein the predriver generates a voltage high output at the first voltage level and the core circuit generates a voltage high output at a second voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
a pull-up driver coupled between the pin and the first supply; and
a pull-down driver coupled between the pin and ground.
-
-
4. The integrated circuit of claim 3 wherein the pull-up driver is a p-channel transistor with a body connection coupled to the first noisy supply.
-
5. The integrated circuit of claim 3 wherein in response to the voltage high output from the core circuit, the predriver generates a low voltage output to turn on the pull-up driver, coupling the pin to the first noisy supply.
-
6. The integrated circuit of claim 1 wherein the level shifting predriver comprises:
-
a first transistor coupled between the first quiet supply and a predriver output node;
a second transistor coupled between the predriver output node and a second supply, wherein control electrodes of the first and second transistors are coupled together and to an intermediate input node;
a third transistor coupled between the first quiet supply and the intermediate input node; and
a fourth transistor coupled between the intermediate input node and the second supply, wherein control electrodes of the third and fourth transistors are coupled together, and coupled to the predriver output node.
-
-
7. The integrated circuit of claim 6 further comprising a fifth transistor coupled between the core circuit and the intermediate input node.
-
8. The integrated circuit of claim 7 wherein the fifth transistor has a control electrode coupled to the first node.
-
9. The integrated circuit of claim 7 wherein the second, fourth, and fifth transistors are similar device types.
-
10. The integrated circuit of claim 6 wherein the first, second, third, and fourth transistors are thick oxide devices.
-
11. The integrated circuit of claim 6 wherein the first and third transistors are PMOS devices with well connections coupled to the first quiet supply.
-
12. The integrated circuit of claim 6 wherein the first and third transistors are floating well PMOS devices.
-
13. An integrated circuit comprising:
-
a output driver coupled between a first supply at a first voltage level and a pin;
a voltage down converter coupled between a second supply and a first node, the first node being at a second voltage level, wherein the second voltage level is lower than the first voltage level;
a core circuit coupled to the first node, wherein the core circuit comprises a memory cell; and
a level shifting predriver, coupled between a control electrode of the output driver and the core circuit, wherein the predriver generates a voltage high output at the first voltage level and the core circuit generates a voltage high output at a second voltage level. - View Dependent Claims (14)
-
-
15. A programmable logic integrated circuit comprising:
-
a programmable logic core; and
an interface circuit coupled to the programmable logic core, the interface circuit comprising;
a first PMOS transistor coupled to receive output signals from the core, the first PMOS transistor having a first terminal coupled to a first supply, a second terminal coupled a pin, and a body bias terminal;
a second PMOS transistor having a gate coupled to the pin, a first terminal coupled to the first supply, and a second terminal coupled to the body bias terminal;
a third PMOS transistor having a gate coupled to the first supply, a first source terminal coupled to the pin, and a second drain terminal coupled to the body bias terminal of the first PMOS transistor; and
a fourth PMOS transistor having a first terminal coupled to the gate of the first PMOS transistor for raising the voltage on the gate of the first PMOS transistor above the supply voltage when the voltage on the pin is larger than the supply voltage. - View Dependent Claims (16, 17, 18)
an input buffer comprising a PMOS transistor coupled to the supply and an NMOS transistor coupled to ground; and
an impedance element coupled between the pin and an input node to the input buffer.
-
-
17. The programmable logic integrated circuit of claim 15 wherein the fourth PMOS transistor includes a gate coupled to a reference voltage.
-
18. The programmable logic integrated circuit of claim 17 wherein the reference voltage is the supply.
-
19. An integrated circuit comprising:
-
an output driver coupled between a first supply and a pin;
a voltage down converter coupled between the first supply and a first node, wherein a voltage level at the first node is a level below the first supply;
a core circuit coupled to the first node, wherein the core circuit comprises programmable logic; and
a level shifting predriver, coupled between a control electrode of the output driver and the core circuit, wherein the predriver generates a voltage high output at the level of the first supply and the core circuit generates a voltage high output at a level at the first node. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
a pull-up driver coupled between the pin and the first supply; and
a pull-down driver coupled between the pin and ground.
-
-
22. The integrated circuit of claim 21 wherein the pull-up driver is a p-channel transistor with a body connection coupled to the first supply.
-
23. The integrated circuit of claim 19 wherein in response to the voltage high output from the core circuit, the predriver generates a low voltage output to turn on the output driver, coupling the pin to the first supply.
-
24. The integrated circuit of claim 19 wherein the level shifting predriver comprises:
-
a first transistor coupled between the first supply and a predriver output node;
a second transistor coupled between the predriver output node and a second supply, wherein control electrodes of the first and second transistors are coupled together and to an intermediate input node;
a third transistor coupled between the first supply and the intermediate input node; and
a fourth transistor coupled between the intermediate input node and the second supply, wherein control electrodes of the third and fourth transistors are coupled together, and coupled to the predriver output node.
-
-
25. The integrated circuit of claim 24 further comprising a fifth transistor coupled between the core circuit and the intermediate input node.
-
26. The integrated circuit of claim 25 wherein the fifth transistor has a control electrode coupled to the first node.
-
27. The integrated circuit of claim 25 wherein the fifth transistor has a control electrode coupled to a quiet positive supply.
-
28. The integrated circuit of claim 24 wherein the first, second, third, and fourth transistors are thick oxide devices.
-
29. The integrated circuit of claim 24 wherein the first and third transistors are PMOS devices with well connections coupled to the first supply.
-
30. The integrated circuit of claim 24 wherein the first and third transistors are floating well PMOS devices.
-
31. The integrated circuit of claim 25 wherein the second, fourth, and fifth transistors are similar device types.
-
32. The integrated circuit of claim 19 wherein the voltage down converter further comprises:
-
a first transistor coupled between the first supply and the first node; and
an inverting amplifier coupled between the first node and a second node, wherein the second node is coupled to a control electrode of the first transistor.
-
-
33. The integrated circuit of claim 32 further comprising a clamping circuit coupled between the first supply and the second node.
-
34. The integrated circuit of claim 33 wherein the clamp circuit comprises first and second diodes.
-
35. A programmable logic integrated circuit comprising:
-
a programmable logic core; and
an interface circuit coupled to the programmable logic core, the interface circuit comprising;
a first PMOS transistor coupled to receive output signals from the core, the first PMOS transistor having a first terminal coupled to a first supply, a second terminal coupled a pin, and a body bias terminal;
a second PMOS transistor having a gate coupled to the pin, a first terminal coupled to the first supply, and a second terminal coupled to the body bias terminal;
a third PMOS transistor having a gate coupled to the first supply, a first terminal coupled to the pin, and a second terminal coupled to the body bias terminal; and
a fourth PMOS transistor having a first terminal coupled to the gate of the first PMOS transistor for raising the voltage on the gate of the first PMOS transistor above the supply voltage when the voltage on the pin is larger than the supply voltage, wherein the fourth PMOS transistor includes a gate coupled to a signal from the programmable logic core.
-
Specification