Clock synthesizer with programmable input-output phase relationship
DC CAFC
First Claim
Patent Images
1. A clock circuit, comprising:
- an oscillator, having a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output;
a reference path providing said reference signal from a reference clock input; and
a feedback path providing said feedback signal from the oscillator output;
wherein each of the reference path and the feedback path comprises a programmable delay circuit.
3 Assignments
Litigations
1 Petition
Accused Products
Abstract
A circuit comprising an oscillator, a reference path, and a feedback path. The oscillator may have a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output. The reference path may provide the reference signal from a reference clock input. The feedback path may provide the feedback signal from the oscillator loop output. At least one of the reference path and the feedback path comprises a programmable delay circuit.
44 Citations
20 Claims
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1. A clock circuit, comprising:
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an oscillator, having a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output;
a reference path providing said reference signal from a reference clock input; and
a feedback path providing said feedback signal from the oscillator output;
wherein each of the reference path and the feedback path comprises a programmable delay circuit. - View Dependent Claims (2, 3, 4, 5, 6, 10, 11, 12, 13)
a second oscillator configured to provide a second output; and
a multiplexer configured to select one of the oscillator outputs as a clock output.
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5. The circuit according to claim 3, wherein the logic circuit is further configured to select an input for the feedback path from at least two of the oscillator output, the divided output, and the clock output.
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6. The circuit according to claim 5, wherein the reference path further comprises a reference counter receiving the reference clock input providing said reference signal therefrom, and the feedback path further comprises a feedback counter receiving the feedback path input providing said feedback signal therefrom.
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10. The circuit according to claim 1, wherein said clock circuit comprises a phase locked loop.
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11. The circuit according to claim 1, wherein said clock circuit comprises a delayed-lock loop.
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12. The circuit according to claim 1, wherein said oscillator comprises a ring oscillator.
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13. The circuit according to claim 4, wherein said second oscillator further comprises a phase locked loop.
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7. A circuit comprising:
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means for generating an output in response to (i) a reference input receiving a reference signal and (ii) a feedback input receiving a feedback signal;
means for generating said reference signal from a reference clock input; and
means for generating said feedback signal from the output, wherein each of the reference path and the feedback path comprises a programmable delay circuit.
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8. A method of controlling a clock output, comprising the steps of:
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generating the clock output in response to a reference input and a feedback input; and
delaying each of the reference input and the feedback input by a programmable amount of time to thereby control the clock output. - View Dependent Claims (9, 14, 15, 16, 17, 18, 19, 20)
producing a divided output from an oscillator output.
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18. The method according to claim 17, wherein said method further comprises the steps of:
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generating a second oscillator output; and
selecting one of the oscillator outputs as said clock output.
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19. The method according to claim 18, wherein said wherein said method further comprises the steps of:
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selecting a characteristic or predetermined delay for the programmable amount of time; and
selecting an input for a feedback path from at least two of (i) one of the oscillator outputs, (ii) the divided output, and (iii) the clock output.
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20. The method according to claim 19, wherein said method further comprises the steps of:
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providing a reference signal generated by a reference counter receiving the reference input; and
providing a feedback signal generated by a feedback counter receiving the feedback path input.
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Specification
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Litigation Data
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Current AssigneePLL Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsSevalia, Piyush, Fox, J. Ken
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Primary Examiner(s)Tran, Toan
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Assistant Examiner(s)COX, CASSANDRA F
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Application NumberUS09/366,897Publication NumberTime in Patent Office951 DaysField of Search327/291, 327/105, 327/158, 327/276, 327/299US Class Current327/105CPC Class CodesH03L 2207/10 Indirect frequency synthesi...H03L 7/081 provided with an additional...H03L 7/183 a time difference being use...H03L 7/23 with pulse counters or freq...
