Low dielectric constant etch stop layers in integrated circuit interconnects
DC CAFC- US 6,388,330 B1
- Filed: 02/01/2001
- Issued: 05/14/2002
- Est. Priority Date: 02/01/2001
- Status: Expired due to Term
First Claim
Patent Images
1. An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
a first dielectric layer formed over the semiconductor substrate having a first opening provided therein;
a first conductor core filling the first opening and connected to the semiconductor device;
an etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the etch stop layer having a dielectric constant below 5.5;
a second dielectric layer formed over the etch stop layer and having a second opening provided therein open to the first conductor core;
a second conductor core filling the second opening and connected to the first conductor core.
2 Assignments
Litigations
4 Petitions
Accused Products
Abstract
An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.
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Citations
10 Claims
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1. An integrated circuit comprising:
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a semiconductor substrate having a semiconductor device provided thereon;
a first dielectric layer formed over the semiconductor substrate having a first opening provided therein;
a first conductor core filling the first opening and connected to the semiconductor device;
an etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the etch stop layer having a dielectric constant below 5.5;
a second dielectric layer formed over the etch stop layer and having a second opening provided therein open to the first conductor core;
a second conductor core filling the second opening and connected to the first conductor core. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit comprising:
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a semiconductor substrate having a semiconductor device provided thereon;
a first dielectric layer formed over the semiconductor substrate having a first opening provided therein;
a first conductor core filling the first opening and connected to the semiconductor device;
a via etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the via etch stop layer having a dielectric constant below 5.5;
a via dielectric layer formed over the via etch stop layer and having a via opening provided therein open to the first conductor core;
a channel etch stop layer of silicon nitride formed over the via dielectric layer, the channel etch stop layer having a dielectric constant below 5.5;
a second dielectric layer formed over the via dielectric layer and having a second opening provided therein open to the via opening; and
a second conductor core filling the via and second openings and connected to the first conductor core. - View Dependent Claims (7, 8, 9, 10)
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Specification