IO power management: synchronously regulated output skew
DC
First Claim
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1. A synchronously regulated output skew circuit comprising an output data array coupled to an array of gates, an output of each element in the output data array being coupled to a corresponding input of a gate in the array of gates, wherein gates in the array of gates are triggered in a phased manner with respect to one another, and wherein the output data array is comprised of a simultaneously enabled array of elements.
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Abstract
An integrated circuit device with reduced noise is described. In traditional simultaneous output switching integrated circuits the noise is proportional to the number of concurrently switching outputs. This excessive supply noise can cause the integrated circuit to malfunction through the loss of data. In the present invention, switching supply noise is reduced in the device without increasing the number of input-output pins by synchronously skewing the output driver. In a preferred embodiment, flip-flops are used to control the phase of the switching outputs in order to reduce the noise and instantaneous power by the number of phase assignments.
57 Citations
20 Claims
- 1. A synchronously regulated output skew circuit comprising an output data array coupled to an array of gates, an output of each element in the output data array being coupled to a corresponding input of a gate in the array of gates, wherein gates in the array of gates are triggered in a phased manner with respect to one another, and wherein the output data array is comprised of a simultaneously enabled array of elements.
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5. A synchronously regulated output skew circuit comprising:
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an array of gates;
an output data array coupled to the array of gates; and
an array of output pads coupled to the array of gates, wherein gates in the array of gates are triggered in a phased manner with respect to one another, and wherein the output data array is simultaneously enabled, and wherein outputs from said output data array are coupled to corresponding inputs of gates in the array of gates such that output from the array of gates to the output pads of the bus is skewed. - View Dependent Claims (6)
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7. A driving circuit for a parallel data bus comprising:
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a first array of triggerable gates, the first array of triggerable gates being simultaneously triggered; and
a second array of triggerable gates to store data connected to the parallel bus, wherein a phased clock signal triggers gates in said second array of triggerable gates in a phased manner with respect to one another, and wherein an output of each gate in the first array of triggerable gates is coupled to an input of a corresponding gate in the second array of triggerable gates. - View Dependent Claims (8, 9, 10)
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11. A driving circuit for a parallel data bus comprising:
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a first array of triggerable gates, the first array of triggerable gates being simultaneously triggered; and
a second array of triggerable gates to store data connected to the parallel bus, wherein a phased clock signal triggers gates in said second array of triggerable gates in a phased manner with respect to one another, and wherein an output of the second array of triggerable gates is skewed such that noise in the output of the second array of triggerable gates is reduced. - View Dependent Claims (12)
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13. A method of flowing a plurality of output data signals within a circuit, comprising:
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(a) connecting an array of output signal lines to a first array of flip-flops;
(b) connecting an enable input for each of said first array of flip-flops to a write clock signal line;
(c) simultaneously triggering the first plurality of flip-flops;
(d) connecting the outputs from said first array of flip-flops to the inputs of a second array of flip-flops; and
(e) connecting an enable input for each of the second array of flip-flops to a synchronously skewed, phased clock signal, wherein the synchronously skewed, phased clock signal triggers flip-flops in the second array of flip-flops in a phased manner with respect to one another. - View Dependent Claims (14, 15, 16)
(f) connecting an output from the second array of flip-flops to plurality of buffers.
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15. The method of claim 13 wherein step (a) comprises connecting an array of output signal lines to a first array of type D flip-flops.
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16. The method of claim 13 wherein step (a) comprises connecting an array of output signal lines to a first array of J-K flip-flops.
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17. A circuit comprising:
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a first plurality of gates triggered in a synchronous manner;
a second plurality of gates coupled to the first plurality of gates, the second plurality of gates being triggered in a phased manner with respect to one another, an output of each gate in the first plurality of gates being coupled to an input of a corresponding gate in the second plurality of gates; and
a plurality of buffers coupled to the second plurality of gates.
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18. A driver circuit of a bus, comprising:
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a first plurality of gates triggered in a synchronous manner; and
a second plurality of gates coupled to the first plurality of gates, the second plurality of gates being triggered in a phased manner with respect to one another such that an output of the second plurality of gates is skewed to thereby reduce noise in data transmission signals from the bus. - View Dependent Claims (19)
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20. A circuit coupled to a data bus, comprising:
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a first plurality of gates triggered in a synchronous manner;
a second plurality of gates coupled to the first plurality of gates, the second plurality of gates being triggered in a phased manner with respect to one another, wherein the first plurality of gates holds data from the data bus, and wherein the output from the second plurality of gates is skewed so as to reduce noise in the output from the second plurality of gates.
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Specification
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Litigation Data
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Current AssigneeAvago Technologies International Sales Pte Limited (Broadcom, Inc.)
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Original AssigneeLSI Logic Corporation (Broadcom, Inc.)
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InventorsGodbee, Joy F., Smith, Paul J., Gauvin, Coralyn S.
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Primary Examiner(s)Wells, Kenneth B.
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Application NumberUS09/157,214Time in Patent Office1,474 DaysField of Search327/141, 327/161-163, 327/258, 327/259, 327/291, 327/295, 327/296US Class Current327/161CPC Class CodesH03L 7/00 Automatic control of freque...
