Semiconductor device
DC
First Claim
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1. A semiconductor device comprising:
- a semiconductor substrate including a substrate region containing a dopant of a first conductivity type;
a gate insulating film and a gate electrode formed on the substrate region;
an on-gate protective layer formed on the gate electrode;
an insulator sidewall formed on respective sides of the gate electrode and the on-gate protective layer and the on-gate protective layer and under the gate insulating film, the insulator sidewall having an L-shape cross section;
doped regions formed respectively on both sides of the insulator sidewall in the semiconductor substrate, the doped regions containing a dopant of a second conductivity type;
an overall protective film covering the doped regions, the on-gate protective layer and the insulator sidewall having an L-shaped cross section;
an interlevel dielectric film formed over the overall protective film and made of an insulating material that is able to be etched selectively with respect to the overall protective film;
openings formed through the interlevel dielectric film and the overall protective film to reach the respective doped regions; and
plug electrodes filing the openings and made of a conductive material, wherein the overall protective film is directly formed over an inside a surface of the insulator sidewall having an L-shaped cross section.
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Accused Products
Abstract
After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in. Accordingly, it is possible to provide a method for fabricating a semiconductor device contributing to device miniaturization without causing a shortcircuit between the gate electrode and a contact member.
50 Citations
16 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate including a substrate region containing a dopant of a first conductivity type;
a gate insulating film and a gate electrode formed on the substrate region;
an on-gate protective layer formed on the gate electrode;
an insulator sidewall formed on respective sides of the gate electrode and the on-gate protective layer and the on-gate protective layer and under the gate insulating film, the insulator sidewall having an L-shape cross section;
doped regions formed respectively on both sides of the insulator sidewall in the semiconductor substrate, the doped regions containing a dopant of a second conductivity type;
an overall protective film covering the doped regions, the on-gate protective layer and the insulator sidewall having an L-shaped cross section;
an interlevel dielectric film formed over the overall protective film and made of an insulating material that is able to be etched selectively with respect to the overall protective film;
openings formed through the interlevel dielectric film and the overall protective film to reach the respective doped regions; and
plug electrodes filing the openings and made of a conductive material, wherein the overall protective film is directly formed over an inside a surface of the insulator sidewall having an L-shaped cross section. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
each of the openings is formed so as to expose a part of the on-gate protective layer and a part of the insulator sidewall, and another sidewall made of the covered insulating film is formed on the side of the part of the insulator sidewall exposed in the respective openings. -
6. The device of claim 1 further comprising doped regions for preventing leakage formed under the doped regions and in a side of the insulator sidewall in the substrate region, the doped regions for preventing leakage containing a dopant of a second conductivity at a lower concentration than that of the doped regions.
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7. The device of claim 1 further comprising a silicide layer formed on the doped regions.
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8. The device of claim 1, wherein the gate insulating film extends to be sandwiched between the insulator sidewall and the semiconductor substrate.
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9. A semiconductor device comprising;
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a gate insulating film and a gate electrode formed over a semiconductor substrate;
an insulator sidewall formed at least over respective sides of the gate electrode over the semiconductor substrate, the insulator sidewall having an L-shape cross section;
an overall protective film covering the semiconductor substrate where the gate electrode and the insulator sidewall are formed; and
an interlevel dielectric film formed over the overall protective film and made of an insulating material that is able to be etched selectively with respect to the overall protective film, wherein the overall protective film is directly formed over an inside surface of the insulator sidewall having an L-shape cross-section. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
at least a doped region formed in the semiconductor substrate arranged on a side of the insulator sidewall;
at least an opening formed through the interlevel dielectric film and the overall protective film to reach the doped region; and
at least a plug electrode filing the opening and made of a conductive material.
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11. The device of claim 10 further comprising a silicide layer formed on the doped region.
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12. The device of claim 9, wherein the gate insulating film extends to be sandwiched between the insulator sidewall and the semiconductor substrate.
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13. The device of claim 9, wherein the interlevel dielectric film is flattened on the surface.
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14. The device of claim 9 further comprising:
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the semiconductor substrate containing a dopant of a first conductivity type;
lightly-doped regions respectively formed between a portion under the gate electrode and the doped layer in the semiconductor substrate, the lighty-doped regions containing a dopant of a second conductivity type at a lower concentration than that of the doped regions.
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15. The device of claim 14 further comprising pocket diffusion regions formed under the lighty-doped regions in the semiconductor substrate, the pocket diffusion regions containing a dopant of a first conductivity type.
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16. The device of claim 9, wherein the insulator sidewall is composed of a non-doped oxide film and the overall protective film is composed of silicon nitride.
Specification
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Litigation Data
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsShimizu, Tadami, Ueda, Takehiko, Obata, Tatsuya, Akamatsu, Susumu, Kato, Yoshiaki, Hibi, Toshitaka, Shimazaki, Toyoyuki
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Primary Examiner(s)Nelms, David
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Assistant Examiner(s)Le, Dung Anh
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Application NumberUS09/714,130Time in Patent Office753 DaysField of Search257/408, 257/384, 257/344, 257/366, 257/405, 257/406, 257/410, 257/346US Class Current257/192CPC Class CodesH01L 21/76897 Formation of self-aligned v...H01L 21/823475 interconnection or wiring o...H01L 29/1045 the doping structure being ...H01L 29/665 using self aligned silicida...H01L 29/6653 using the removal of at lea...H01L 29/66598 forming drain [D] and light...H01L 29/7833 with lightly doped drain or...Y10S 257/90 MOSFET type gate sidewall i...
