Integrated circuit having buffering circuitry with slew rate control
DC
First Claim
Patent Images
1. Circuitry formed on an integrated circuit, the circuitry comprising:
- a first terminal;
a second terminal;
a first transistor having a first body, a first control electrode, a first source region, and a first drain region, wherein;
the first body, the first source region, and the first drain region are shorted together and are coupled to the first terminal; and
a second transistor having a second body, a second control electrode, a second source region, and a second drain region, wherein;
the second body, the second source region, and the second drain region are shorted together and are coupled to the second terminal, the second control electrode is coupled to the first control electrode, and the second transistor is of a same conductivity type as the first transitor.
18 Assignments
Litigations
0 Petitions
Accused Products
Abstract
Buffering circuitry (10) uses pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) to control the rising and falling slew rates of an output signal (50) provided by buffering circuitry (10). Pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) may be used in an embodiment of buffering circuitry (10) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry (10) utilizes distributed resistive elements (89-91) to provide improved electrostatic discharge protection. Buffering circuitry (10) utilizes a low power level shifter (16). Voltage reference generation circuitry (18) may be used to provide a stable low power reference voltage VREF (42).
40 Citations
15 Claims
-
1. Circuitry formed on an integrated circuit, the circuitry comprising:
-
a first terminal;
a second terminal;
a first transistor having a first body, a first control electrode, a first source region, and a first drain region, wherein;
the first body, the first source region, and the first drain region are shorted together and are coupled to the first terminal; and
a second transistor having a second body, a second control electrode, a second source region, and a second drain region, wherein;
the second body, the second source region, and the second drain region are shorted together and are coupled to the second terminal, the second control electrode is coupled to the first control electrode, and the second transistor is of a same conductivity type as the first transitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
a PMOS transistor having a control electrode, a first source/drain region, and a second source/drain region, a first NMOS transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the control electrode of the first NMOS transistor is coupled to the control electrode of the PMOS transistor, and a second NMOS transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the control electrode of the second NMOS transistor is coupled to the first control electrode of the first transistor and the second control electrode of the second transistor, and the second source/drain region of the PMOS transistor is coupled to the first source/drain region of the second NMOS transistor and the first source/drain region of the first NMOS transistor is coupled to the second source/drain region of the second NMOS transistor. -
5. The integrated circuit of claim 3, wherein the voltage clamping circuitry is further characterized as comprising
a first NMOS transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the control electrode of the first NMOS transistor is coupled to the first control electrode of the first transistor and the second control electrode of the second transistor, a second NMOS transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the control electrode of the second NMOS transistor is coupled to the second source/drain region of the second NMOS transistor and the first source/drain region of the second NMOS transistor is coupled to the second source/drain region of the first NMOS transistor, and a third NMOS transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the control electrode of the third NMOS transistor is coupled to the second source/drain region of the third NMOS transistor and the first source/drain region of the third NMOS transistor is coupled to the second source/drain region of the second NMOS transistor. -
6. The integrated circuit of claim 1, wherein the circuitry further comprises:
-
a third transistor having a third control electrode, a third source region, and a third drain region, wherein the third control electrode is coupled to the first terminal; and
a fourth transistor having a fourth control electrode, a fourth source region, and a fourth drain region, wherein the fourth source region is coupled to the third drain region of the third transistor.
-
-
7. The integrated circuit of claim 6, wherein the buffer circuitry further comprises voltage reference generation circuitry having an output, wherein the output of the voltage reference generation circuitry is coupled to the fourth control electrode of the fourth transistor.
-
8. The integrated circuit of claim 7, wherein the voltage reference generation circuitry is further characterized as comprising
a first resistive element having a first terminal and a second terminal, wherein the first terminal is coupled to a first voltage and the second terminal is coupled to the output of the voltage reference generation circuitry, a first capacitive element having a first terminal and a second terminal, wherein the first terminal is coupled to the first voltage and the second terminal is coupled to the output of the voltage reference generation circuitry, a second resistive element having a first terminal and a second terminal, wherein the first terminal is coupled to a second voltage and the second terminal is coupled to the output of the voltage reference generation circuitry, a second capacitive element having a first terminal and a second terminal, wherein the first terminal is coupled to the second voltage and the second terminal is coupled to the output of the voltage reference generation circuitry. -
9. The integrated circuit of claim 8, wherein the voltage reference generation circuitry further comprises
a fifth transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the first source/drain region is coupled to the first voltage, a third resistive element having a first terminal and a second terminal, wherein the first terminal is coupled to the second source/drain region of the fifth transistor and the second terminal is coupled to the output of the voltage reference generation circuitry, a fourth resistive element having a first terminal and a second terminal, wherein the first terminal is coupled to the output of the voltage reference generation circuitry, a sixth transistor having a control electrode, a first source/drain region, and a second source/drain region, wherein the first source/drain region is coupled to the second terminal of the fourth resistive element and the control electrode is coupled to a low power stop control signal. -
10. The integrated circuit of claim 9, wherein the third resistive element is further characterized as a third plurality of transistors connected in series.
-
11. The integrated circuit of claim 1, wherein circuitry is further characterized as buffer circuitry, and wherein the buffer circuitry further comprises:
-
an input/output pad;
a plurality of transistors, each of the plurality of transistors having a source region and a drain region, wherein the source region of each transistor in the plurality of transistors is coupled to the third drain region of the third transistor; and
a plurality of resistors, each resistor in the plurality of resistors having a first terminal and a second terminal, wherein the first terminal of each resistor in the plurality of resistors is coupled to the input/output pad and the drain region of each transistor in the plurality of transistors is coupled to the second terminal of one resistor.
-
-
12. The integrated circuit of claim 1, wherein the first transistor and the second transistor are further characterized as PMOS transistors.
-
13. The integrated circuit of claim 12, wherein:
-
the first control electrode of the first transistor is further characterized as a first gate electrode;
the second control electrode of the second transistor is further characterized as a second gate electrode; and
the first gate electrode is connected to the second gate electrode.
-
-
14. The integrated circuit of claim 1, wherein the first transistor and the second transistor are further characterized as NMOS transistors.
-
15. The integrated circuit of claim 14, wherein:
-
the first control electrode of the first transistor is further characterized as a first gate electrode;
the second control electrode of the second transistor is further characterized as a second gate electrode; and
the first gate electrode is connected to the second gate electrode.
-
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
Litigation Data
-
Current AssigneeNorth Star Innovations Inc. (Wi-LAN Inc.)
-
Original AssigneeMotorola, Inc. (Motorola Solutions, Inc.)
-
InventorsWhatley, Roger A., Pappert, Bernard J.
-
Primary Examiner(s)Lee, Eddie
-
Assistant Examiner(s)Fenty, Jesse A.
-
Application NumberUS09/479,093Time in Patent Office1,068 DaysField of Search257/355, 257/356, 257/357, 257/360, 257/546, 257/348, 361/100, 361/101US Class Current257/355CPC Class CodesG05F 3/242 with compensation for devic...H03K 19/00315 in field-effect transistor ...H03K 19/00361 in field effect transistor ...
