Display system having floating point rasterization and floating point framebuffering
DC
First Claim
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1. A computer system, comprising:
- a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer;
wherein the rasterization circuit performs scan conversion on vertices having floating point color values.
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Abstract
A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.
134 Citations
31 Claims
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1. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer;
wherein the rasterization circuit performs scan conversion on vertices having floating point color values.
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2. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values;
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer;
a texture circuit coupled to the rasterization circuit that applies a texture to the primitive, wherein the texture is specified by floating point values; and
a texture memory coupled to the texture circuit that stores a plurality of textures in floating point values.
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3. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer;
wherein the floating point format is comprised of sixteen bits in a s10e5 format.
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4. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values;
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; and
a fog circuit coupled to the rasterization circuit for performing a fog function, wherein the fog function operates on floating point color values.
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5. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values;
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; and
a blender coupled to the rasterization circuit which blends floating point color values.
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6. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values;
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; and
logic coupled to the rasterization circuit which performs per-fragment operations on floating point color values.
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7. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and
a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer;
wherein the processor, the rasterization circuit, and the frame buffer are on a single semiconductor chip. - View Dependent Claims (8)
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9. In a computer system, a method for rendering a three-dimensional image for display, comprising the steps of:
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performing geometric calculations on a plurality of vertices of a plurality of polygons;
scan converting a plurality of pixels according to the vertices, wherein scan conversion is performed on floating point color values;
applying a texture to the image by reading floating point texture values stored in a texture memory;
simulating fog effects, wherein fog is simulated by modifying floating point color values;
drawing the image for display on a display screen coupled to the computer system. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
reading data from the frame buffer;
modifying the data;
writing modified data back to the frame buffer.
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16. The method of claim 10 further comprising the step of modifying color values for lighting, wherein lighting calculations operate on floating point color values.
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17. In a computer system, a method for operating on data stored in a frame buffer, comprised of:
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storing the data in the frame buffer in a floating point format;
reading the data from the frame buffer in the floating point format;
operating directly on the data in the floating point format; and
writing the data to the frame buffer in the floating point format;
wherein the steps of writing, storing, and reading the data in the frame buffer in the floating point format are further comprised of a specification of the floating point format, wherein the specification corresponds to a level of range and precision. - View Dependent Claims (18, 19, 20, 21)
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22. A computer system having a floating point frame buffer for storing a plurality of floating point color values;
wherein the floating point color values are written to, read from, and stored in the frame buffer using a specification of the floating point color values that corresponds to a level of range and precision. - View Dependent Claims (23, 24)
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25. A computer system, comprising:
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a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on an s10e5 floating point format;
a frame buffer coupled to the rasterization circuit for storing a plurality of s10e5 floating point color values;
a display screen coupled to the frame buffer for displaying an image according to the s10e5 color values stored in the frame buffer. - View Dependent Claims (26, 27, 28, 29, 30, 31)
a texture circuit coupled to the rasterization circuit that applies a texture to the primitive, wherein the texture is specified by s10e5 floating point values.
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27. The computer system of claim 25 further comprising a lighting circuit coupled to the rasterization circuit for performing a lighting function, wherein the lighting function executes on s10e5 floating point color values.
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28. The computer system of claim 25 further comprising a fog circuit coupled to the rasterization circuit for performing a fog function, wherein the fog function operates on s10e5 floating point color values.
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29. The computer system of claim 25 further comprising an antialiasing circuit coupled to the rasterization circuit which performs an antialiasing algorithm on s10e5 floating point color values.
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30. The computer system of claim 25 further comprising a blender coupled to the rasterization circuit which blends s10e5 floating point color values.
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31. The computer system of claim 25 further comprising logic coupled to the rasterization circuit which performs per-fragment operations on s10e5 floating point color values.
Specification
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Litigation Data
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Current AssigneeRPX Corporation
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Original AssigneeSilicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
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InventorsAirey, John M., Peercy, Mark S., Drebin, Robert A., Montrym, John, Dignam, David L., Migdal, Christopher J., Loh, Danny D.
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Primary Examiner(s)Powell, Mark R.
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Assistant Examiner(s)HAVAN, THU THAO
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Application NumberUS09/098,041Time in Patent Office1,981 DaysField of Search345/431, 345/520, 345/523, 345/422, 345/503, 345/153, 345/502, 345/426, 345/430, 345/196, 345/950, 708/606, 708/512, 365/189.05, 365/230.08, 326/62, 375/372, 348/419US Class Current345/520CPC Class CodesG06T 1/20 Processor architectures; Pr...G06T 11/40 Filling a planar surface by...G06T 15/00 3D [Three Dimensional] imag...G06T 15/405 using Z-bufferG06T 17/00 Three dimensional [3D] mode...G06T 19/00 Manipulating 3D models or i...G09G 5/393 Arrangements for updating t...
