Circuit(s), method(s) and architecture for configurable packet re-timing in network repeater hubs
DC
First Claim
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1. A circuit comprising:
- a first circuit configured to send a plurality of packets of information, each of said packets being sent in response to (i) a plurality of receive data packets and (ii) a delay control signal, wherein said delay control signal configures a delay between receiving one of said receive data packets and sending one of said plurality of packets; and
a state machine configured to adjust and present said delay control signal, wherein said state machine adjusts said delay during an idle state of said first circuit.
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Abstract
A circuit comprising a first circuit and a second circuit. The first circuit may be configured to present information after a delay in response to a plurality of transmit and receive inputs. The second circuit may be configured to adjust the amount of delay prior to presenting information. The second circuit may be implemented as a state machine.
11 Citations
14 Claims
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1. A circuit comprising:
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a first circuit configured to send a plurality of packets of information, each of said packets being sent in response to (i) a plurality of receive data packets and (ii) a delay control signal, wherein said delay control signal configures a delay between receiving one of said receive data packets and sending one of said plurality of packets; and
a state machine configured to adjust and present said delay control signal, wherein said state machine adjusts said delay during an idle state of said first circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer readable medium containing instructions for configuring a delay in a network repeater comprising the steps of:
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(a) receiving a plurality of data packets from a physical layer device;
(b) configuring a start of packet delay;
(c) sending a plurality of said data packets after said start of packet (SOP) delay;
(d) prior to step (b), generating a data packet preamble; and
(e) repeating steps (a), (b), and (c) during each idle state of said repeater. - View Dependent Claims (8, 9, 10)
(f) executing a collision detection and retransmit protocol after step (c).
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9. The method according to claim 7, wherein said computer readable medium is stored on a state machine.
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10. The method according to claim 7, wherein said step of configuring said delay responds to configuration information received from a management bus.
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11. A method for dynamically configuring a delay in a network repeater comprising the steps of:
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(a) receiving a plurality of data packets from a physical layer device;
(b) configuring a start of packet delay;
(c) sending a plurality of said data packets after said start of packet (SOP) delay;
(d) prior to step (b), generating a data packet preamble; and
(e) repeating steps (a), (b), and (c) during each idle state of said repeater. - View Dependent Claims (12, 13)
(e) executing a collision detection and retransmit protocol after step (c).
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13. The method according to claim 11, wherein said step of configuring said delay responds to configuration information received from a management bus.
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14. A circuit comprising:
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a first circuit configured to send a plurality of packets of information, each of said packets being sent in response to (i) a plurality of receive data packets and (ii) a delay control signal, wherein (a) said delay control signal configures a delay between receiving one of said receive data packets and sending one of said plurality of packets and (b) said delay comprises a fixed delay plus a programmable delay;
a second circuit configured to adjust and present said delay control signal; and
a FIFO having a read pointer and a write pointer, said FIFO being coupled between a shared bus and said first circuit, wherein the distance between said read and write pointer are adjusted in response to said delay.
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Specification
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Litigation Data
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Current AssigneeGordium Innovations LLC
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsMatthews, Joe P.
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Primary Examiner(s)Pezzlo, John
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Application NumberUS08/935,982Time in Patent Office2,345 DaysField of Search370/445, 370/446, 370/447, 370/448, 370/517, 370/407, 370/408, 370/501, 370/315, 370/508, 370/516, 370/419, 370/463, 370/502, 370/519, 375/211US Class Current370/517CPC Class CodesH04J 3/0632 Synchronisation of packets ...
