Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby
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First Claim
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1. A method of making a memory device, comprising the steps of:
- forming a plurality of memory cells in a memory portion of a semiconductor substrate, wherein the formation of each of the memory cells includes the steps of;
forming a floating gate of conductive material disposed over and insulated from the memory portion of the substrate, and forming a control gate of conductive material disposed over and insulated from the memory portion of the substrate;
forming a layer of protective material over the control gates;
forming a plurality of logic devices in a peripheral region of the semiconductor substrate after the formation of the protective material layer, wherein the formation of each of the logic devices includes the step of forming a block of conductive material disposed over and insulated from the peripheral region of the substrate, and wherein the formation of the blocks of conductive material includes the formation of residual conductive material on the layer of protective material; and
removing the residual conductive material without removing the conductive material of the control gates.
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Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. The control gate polysilicon is formed over the substrate, and protected by a layer of protective material, before the formation of other polysilicon elements associated with the memory array, to ensure the proper remove of residual polysilicon stringers.
50 Citations
10 Claims
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1. A method of making a memory device, comprising the steps of:
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forming a plurality of memory cells in a memory portion of a semiconductor substrate, wherein the formation of each of the memory cells includes the steps of;
forming a floating gate of conductive material disposed over and insulated from the memory portion of the substrate, and forming a control gate of conductive material disposed over and insulated from the memory portion of the substrate;
forming a layer of protective material over the control gates;
forming a plurality of logic devices in a peripheral region of the semiconductor substrate after the formation of the protective material layer, wherein the formation of each of the logic devices includes the step of forming a block of conductive material disposed over and insulated from the peripheral region of the substrate, and wherein the formation of the blocks of conductive material includes the formation of residual conductive material on the layer of protective material; and
removing the residual conductive material without removing the conductive material of the control gates. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
forming the protective material layer over both the memory and peripheral portions of the substrate, and removing a portion of the protective material layer formed over the peripheral portion of the substrate.
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7. The method of claim 1, wherein for each of the memory cells, the protective material layer includes a vertical portion that extends up and over the control gate.
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8. The method of claim 7, wherein for each of the memory cells, the residual conductive material is formed laterally adjacent to the vertical portion of the protective material layer.
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9. The method of claim 8, wherein for each of the memory cells, the residual conductive material is formed as a spacer of the conductive material.
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10. The method of claim 1, wherein for each of the memory cells, the control gate is formed as a spacer of the conductive material.
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Litigation Data
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Current AssigneeSilicon Storage Technology Incorporated (Microchip Technology Incorporated)
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Original AssigneeSilicon Storage Technology Incorporated (Microchip Technology Incorporated)
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InventorsWang, Chih Hsin
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Primary Examiner(s)Nelms, David
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Assistant Examiner(s)Le, Thao P.
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Application NumberUS10/205,289Publication NumberTime in Patent Office678 DaysField of Search438/257, 438/258US Class Current438/257CPC Class CodesG11C 16/0425 comprising cells containing...H01L 27/105 including field-effect comp...H01L 29/40114 the electrodes comprising a...H10B 41/40 characterised by the periph...H10B 41/48 with a tunnel dielectric la...
