Semiconductor integrated circuit device and method for fabricating the same
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First Claim
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1. A semiconductor integrated circuit device comprising:
- a first circuit pattern having a first linear pattern and placed in a region in which a group of elements having a repetitive pattern are formed; and
a second circuit pattern having a second linear pattern and placed in a region in which components other than the group of elements are formed, a dummy pattern being inserted in the region in which the second circuit pattern is placed such that a sum perimeter of the first linear pattern, the second linear pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first linear pattern per unit area.
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Abstract
Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.
118 Citations
6 Claims
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1. A semiconductor integrated circuit device comprising:
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a first circuit pattern having a first linear pattern and placed in a region in which a group of elements having a repetitive pattern are formed; and
a second circuit pattern having a second linear pattern and placed in a region in which components other than the group of elements are formed, a dummy pattern being inserted in the region in which the second circuit pattern is placed such that a sum perimeter of the first linear pattern, the second linear pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first linear pattern per unit area. - View Dependent Claims (2, 3)
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4. A semiconductor integrated circuit device comprising:
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a first circuit pattern having a first gate electrode pattern and placed in a memory circuit region; and
a second circuit pattern having a second gate electrode pattern and placed in a logic circuit region, a dummy pattern being inserted in the logic region in which the second circuit pattern is placed such that a sum perimeter of the first gate electrode pattern, the second gate electrode pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first gate electrode pattern per unit area. - View Dependent Claims (5, 6)
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Specification
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Litigation Data
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsTamaki, Tokuhiko, Kawashima, Koichi, Sakurai, Yasuo, Tateiwa, Kenji
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Primary Examiner(s)DEO, DUY VU NGUYEN
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Application NumberUS09/964,868Publication NumberTime in Patent Office1,089 DaysField of Search257/41, 257/2, 257/202-211, 257/390, 257/401US Class Current257/41CPC Class CodesH01L 21/32137 of silicon-containing layersH01L 21/32139 using masks
