Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system
DC
First Claim
Patent Images
1. A phase locked loop circuit comprising:
- a signal generator; and
a spread spectrum modulator coupled to the signal generator, wherein the spread spectrum modulator comprises at least one selector, wherein the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator and further wherein the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage.
1 Assignment
Litigations
0 Petitions
Accused Products
Abstract
A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.
40 Citations
31 Claims
-
1. A phase locked loop circuit comprising:
-
a signal generator; and
a spread spectrum modulator coupled to the signal generator, wherein the spread spectrum modulator comprises at least one selector, wherein the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator and further wherein the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
a buffer coupled to the voltage divider;
a waveform generator coupled to the plurality of multiplexers;
a voltage adder coupled to the plurality of multiplexers and the buffer; and
a voltage subtracter coupled to the voltage adder and the waveform generator.
-
-
6. The phase locked loop circuit of claim 5, wherein the waveform generator comprises:
-
a first comparator, wherein the first comparator compares a voltage at an output node of the waveform generator with the high voltage;
a second comparator, wherein the second comparator compares the voltage at the output node with the low voltage;
a flip-flop coupled to the first and second comparators;
a first switch coupled to a first output node of the flip-flop; and
a second switch coupled to a second output node of the flip-flop;
a first current source coupled to the first switch, the first current source for increasing current at the output node; and
a second current source coupled to the second switch, the second current source for sinking current from the output node.
-
-
7. The phase locked loop circuit of claim 6, wherein the waveform generator is programmable to provide different spread rates.
-
8. The phase locked loop circuit of claim 6, wherein the voltage adder comprises an operational amplifier, wherein the voltage adder receives the reference voltage and an output of the buffer at a positive input node and provides a voltage adder output that is a sum of the reference voltage and the output of the buffer.
-
9. The phase locked loop circuit of claim 8, wherein the voltage subtracter comprises an operational amplifier, wherein the voltage subtracter subtracts the voltage at the output node of the waveform generator from the voltage adder output.
-
10. The phase locked loop circuit of claim 1, wherein the spread spectrum modulator comprises a waveform generator.
-
11. The phase locked loop circuit of claim 10, wherein the waveform generator comprises:
-
a first comparator, wherein the first comparator compares a voltage at an output node of the waveform generator with a high voltage;
a second comparator, wherein the second comparator compares the voltage at the output node with a low voltage;
a flip-flop coupled to the first and second comparators;
a first switch coupled to a first output node of the flip-flop; and
a second switch coupled to a second output node of the flip-flop;
a first current source coupled to the first switch, the first current source for increasing current at the output node; and
a second current source coupled to the second switch, the second current source for sinking current from the output node.
-
-
12. The phase locked loop circuit of claim 10, wherein the spread spectrum modulator further comprises:
-
a voltage subtracter coupled to the waveform generator; and
a voltage adder coupled to the voltage subtracter.
-
-
13. A digital system including a programmable logic device and the phase locked loop circuit of claim 1.
-
14. A programmable logic device including the phase locked loop circuit of claim 1.
- 15. A phase locked loop circuit comprising a spread spectrum modulator, the spread spectrum modulator comprising a voltage divider and a selector coupled to the voltage divider, wherein the selector selects a plurality of voltages that correspond to a spread rate and percentage of spread for the spread spectrum modulator.
-
24. A method of providing an output clock signal, the method comprising:
-
spreading a control voltage utilizing an analog voltage controlled spread spectrum modulator to provide a spread spectrum control voltage, wherein the spreading comprises selecting a plurality of voltage levels that correspond to a spread rate and percentage of spread; and
generating an output clock signal in response to the spread spectrum control voltage. - View Dependent Claims (25, 26, 27)
dividing the control voltage to provide the plurality of voltage levels;
selecting a high voltage, a low voltage, and a reference voltage from the plurality of voltage levels;
generating a voltage waveform in response to the high voltage and the low voltage;
adding the reference voltage with a buffered version of the control voltage to provide a sum voltage; and
subtracting the voltage waveform from the sum voltage to provide the spread spectrum control voltage.
-
-
26. The method of claim 25 further comprising:
comparing a feedback clock signal with a reference clock signal to provide the control voltage.
-
27. The method of claim 24, wherein the spreading comprises:
-
generating a voltage waveform in response to a high voltage and a low voltage;
adding a reference voltage with the control voltage to provide a sum voltage; and
subtracting the voltage waveform from the sum voltage to provide the spread spectrum control voltage.
-
-
28. A phase locked loop comprising:
-
means for spreading a control voltage, wherein said means for spreading comprises;
a means for selecting, further wherein said means for spreading uses analog voltage controlled spread spectrum modulation and provides a spread spectrum control voltage;
means for dividing the control voltage to provide a plurality of voltage levels, wherein the means for dividing is coupled to the means for selecting, wherein the means for selecting selects a high voltage, a low voltage, and a reference voltage from the plurality of voltage levels;
means for generating a voltage waveform coupled to the means for selecting, wherein the means for generating a voltage waveform generates a voltage waveform in response to the high voltage and the low voltage;
means for adding coupled to the means for selecting, wherein the means for adding adds the reference voltage with a buffered version of the control voltage to provide a sum voltage; and
means for subtracting coupled to the means for adding and the means for generating a voltage waveform, wherein the means for subtracting subtracts the voltage waveform from the sum voltage to provide the spread spectrum control voltage; and
means for generating an output clock signal, wherein the means for generating generates the output clock signal in response to the spread spectrum control voltage. - View Dependent Claims (29)
-
-
30. A phase locked loop circuit comprising:
-
a signal generator;
a spread spectrum modulator coupled to the signal generator, wherein the spread spectrum modulator comprises at least one selector, further wherein the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage;
a detector;
a charge pump filter coupled to the detector and the spread spectrum modulator;
a loop filter coupled to the charge pump and the spread spectrum modulator;
a first divider coupled to the signal generator and a first input node of the detector, wherein the first divider receives a signal generator output signal from the signal generator and provides a first input signal to the first input node of the detector;
a second divider coupled to a second input node of the detector;
a third divider coupled to the signal generator; and
wherein the second divider receives a reference clock signal and provides a second input signal to the second input node of the detector, further wherein the third divider receives the signal generator output signal from the signal generator and provides an output clock signal.
-
-
31. A phase locked loop comprising:
-
means for spreading a control voltage, wherein said means for spreading comprises;
a means for selecting, further wherein said means for spreading uses analog voltage controlled spread spectrum modulation and provides a spread spectrum control voltage;
means for generating a voltage waveform, wherein the means for generating a voltage waveform generates a voltage waveform in response to a high voltage and a low voltage;
means for adding, wherein the means for adding adds a reference voltage with the control voltage to provide a sum voltage; and
means for subtracting coupled to the means for adding and the means for generating a voltage waveform, wherein the means for subtracting subtracts the voltage waveform from the sum voltage to provide the spread spectrum control voltage; and
means for generating an output clock signal, wherein the means for generating generates the output clock signal in response to the spread spectrum control voltage.
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
Litigation Data
-
Current AssigneeAltera Corporation (Intel Corporation)
-
Original AssigneeAltera Corporation (Intel Corporation)
-
InventorsChang, Wanli, Starr, Gregory W.
-
Primary Examiner(s)Callahan, Timothy P.
-
Assistant Examiner(s)Luu, An T.
-
Application NumberUS10/138,461Publication NumberTime in Patent Office879 DaysField of Search331/78, 331/23, 331/18, 331/19, 332/117, 332/120, 332/121, 332/122, 375/200US Class Current331/78CPC Class CodesH03L 7/0896 the current generators bein...H03L 7/0898 the source or sink current ...H03L 7/093 using special filtering or ...H03L 7/18 using a frequency divider o...H03L 7/1803 the counter or frequency di...H03M 1/808 using resistorsH04B 1/707 using direct sequence modul...
