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Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect

DC CAFC
  • US 6,849,946 B2
  • Filed: 02/07/2001
  • Issued: 02/01/2005
  • Est. Priority Date: 08/31/1998
  • Status: Expired due to Term
First Claim
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1. A method, comprising:

  • etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench;

    filling said trenches with a conductive material; and

    polishing said conductive material to form dummy conductors in said laterally spaced dummy trenches and interconnect in said series of second trenches and said first trench, wherein said polishing comprises applying a liquid substantailly free of particulate matter between an abrasive polishing surface and the conductive material.

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