Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
DC CAFCFirst Claim
1. A method, comprising:
- etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench;
filling said trenches with a conductive material; and
polishing said conductive material to form dummy conductors in said laterally spaced dummy trenches and interconnect in said series of second trenches and said first trench, wherein said polishing comprises applying a liquid substantailly free of particulate matter between an abrasive polishing surface and the conductive material.
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Accused Products
Abstract
The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.
112 Citations
22 Claims
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1. A method, comprising:
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etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench;
filling said trenches with a conductive material; and
polishing said conductive material to form dummy conductors in said laterally spaced dummy trenches and interconnect in said series of second trenches and said first trench, wherein said polishing comprises applying a liquid substantailly free of particulate matter between an abrasive polishing surface and the conductive material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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etching a plurality of laterally spaced dummy trenches into a dielectric layer between a trench which is to receive a first interconnect feature and a series of trenches which are to receive a series of second interconnect features, wherein the first interconnect feature is relatively wide compared to each of the series of second interconnect features;
filling said plurality of laterally spaced dummy trenches with a conductive material; and
polishing said conductive material to form dummy conductors, wherein said polishing comprises applying a liquid substantially free of particulate matter between an abrasive polishing surface and the conductive material. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A substantially planar semiconductor topography, comprising:
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a plurality of laterally spaced dummy trenches in a dielectric layer, between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench and wherein a lateral dimension of at least one of the laterally spaced dummy trenches is less than a lateral dimension of the first trench and greater than a lateral dimension of at least one of the series of second trenches;
dummy conductors in said laterally spaced dummy trenches and electrically separate from electrically conductive features below said dummy conductors; and
conductive lines in said series of second trenches and said first trench, wherein upper surfaces of said conductive lines are substantially coplanar with dummy conductor upper surfaces. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification