Programmable loop bandwidth in phase locked loop (PLL) circuit
DCFirst Claim
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1. A phase locked loop circuit comprising:
- a feedback loop; and
a loop filter coupled to the feedback loop, wherein the loop filter is programmable in user mode to provide one of a plurality of bandwidths.
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Abstract
A PLL circuit is described. The PLL circuit includes: a feedback loop and a loop filter coupled to the feedback loop, where the loop filter is programmable to provide one of a plurality of bandwidths. In one embodiment, the loop filter is programmable to provide one of a plurality of resistances, each resistance of the plurality of resistances corresponding to one of the plurality of bandwidths. In one embodiment, the feedback loop includes a detector and a signal generator coupled to the detector.
65 Citations
46 Claims
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1. A phase locked loop circuit comprising:
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a feedback loop; and
a loop filter coupled to the feedback loop, wherein the loop filter is programmable in user mode to provide one of a plurality of bandwidths. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A phase locked loop circuit comprising:
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a signal generator; and
a loop filter coupled to the signal generator, wherein the loop filter is programmable in user mode to provide one of a plurality of bandwidths. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 43, 44)
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40. A method of providing an output clock signal, the method comprising:
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comparing a feedback clock signal with a reference clock signal;
providing a control signal to a signal generator;
selecting in user mode one of a plurality of bandwidths in a loop filter; and
generating an output clock signal in response to the control signal. - View Dependent Claims (41, 42, 45, 46)
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Specification