Double-gate FinFET device and fabricating method thereof
DC CAFC
First Claim
Patent Images
1. A double-gate FinFET device, comprising:
- a bulk silicon substrate;
a Fin active region which is a wall-shape single crystalline silicon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate;
a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate;
a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer;
a first oxide layer which is formed on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide;
a gate which is formed on said first and second oxide layer;
a source/drain region which is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and
a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the thickness of said gate oxide layer is between 0.5 nm and 10 nm, and the thickness of said first oxidation layer is between 0.5 nm and 200 nm.
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Abstract
The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction.
The conventional double-gate MOS devices are fabricated using SOI wafers which are more expensive than bulk silicon wafers. It also has problems including the floating body effects, larger source/drain parasitic resistance, off-current increase, and deterioration in heat transfer to the substrate.
226 Citations
19 Claims
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1. A double-gate FinFET device, comprising:
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a bulk silicon substrate;
a Fin active region which is a wall-shape single crystalline silicon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate;
a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate;
a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer;
a first oxide layer which is formed on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide;
a gate which is formed on said first and second oxide layer;
a source/drain region which is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and
a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the thickness of said gate oxide layer is between 0.5 nm and 10 nm, and the thickness of said first oxidation layer is between 0.5 nm and 200 nm. - View Dependent Claims (2, 3, 4, 5, 6, 11, 12, 14, 15, 16, 17)
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7. A double-gate FinFET device, comprising:
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a bulk silicon substrate;
a Fin active region which is a all-shape single crystalline sililcon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate;
a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate;
a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer;
a first oxide layer which is formed on the upper surface or said Fin active region with a thickness greater or equal to that of the gate oxide;
a gate which is formed on said first and second oxide layer;
a source/drain region whcih is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and
a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the contact resistance is reduced by selecting the size of a contact region which is in contact with said metal layer to be greater than the width of said Fin active region, and/or the length of said gate, and selective epitaxial layer is grown on both sides (source/drain region) of the Fin active region except where said Fin active region overlaps with the gate in a self-aligned manner to the gate, in order to reduce parasitic source/drain resistance. - View Dependent Claims (8, 9, 10, 18, 19)
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13. A double-gate FinFET device, comprising:
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a bulk silicon substrate;
a Fin active region which is a all-shape single crystalline sililcon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate;
a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate;
a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer;
a first oxide layer which is formed on the upper surface or said Fin active region with a thickness greater or equal to that of the gate oxide;
a gate which is formed on said first and second oxide layer;
a source/drain region whcih is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and
a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the resistance of said Fin active region is reduced by enlarging the width of said Fin active region within the oxidation layer as it approaches the bulk silicon substrate.
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Specification
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Litigation Data
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Current AssigneeKIPB LLC (f/k/a KAIST IP US LLC) (P&IB Co. Ltd.)
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Original AssigneeJong Ho Lee
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InventorsLee, Jong-ho
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Primary Examiner(s)WOJCIECHOWICZ, EDWARD JOSEPH
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Application NumberUS10/358,981Publication NumberTime in Patent Office812 DaysField of Search257/308, 257/618, 257/619, 257/620US Class Current257/308CPC Class CodesH01L 2029/7858 having contacts specially a...H01L 29/41791 for transistors with a hori...H01L 29/66795 with a horizontal current f...H01L 29/7851 with the body tied to the s...
