Three terminal noninverting transistor switch
DC CAFC
First Claim
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1. A noninverting transistor switch having only three terminals, said three terminals being a first terminal, a second terminal and a third terminal, said noninverting transistor switch comprising:
- (a) a transistor connected to the second and third terminals, said transistor having an on switching state in which current is able pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals, (b) a voltage stabilizer connected to the second and third terminals, and (c) a complementary metal oxide semiconductor (CMOS) inverter connected to the first terminal, the second terminal, said transistor and said voltage stabilizer, said CMOS inverter interrupting the passing of current between said voltage stabilizer and the second terminal when said transistor is in its off switching state.
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Abstract
A noninverting transistor switch having only a first terminal, a second terminal and a third terminal includes a transistor connected to the second and third terminals, the transistor having an on switching state in which current is able to pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals. The transistor switch also includes a voltage stabilizer connected to the second and third terminals. The transistor switch further includes a CMOS inverter connected to the first terminal, the second terminal, the transistor and the voltage stabilizer. In use, the CMOS inverter interrupts the passing of current between the voltage stabilizer and the second terminal when the transistor is in its off switching state.
7 Citations
19 Claims
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1. A noninverting transistor switch having only three terminals, said three terminals being a first terminal, a second terminal and a third terminal, said noninverting transistor switch comprising:
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(a) a transistor connected to the second and third terminals, said transistor having an on switching state in which current is able pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals, (b) a voltage stabilizer connected to the second and third terminals, and (c) a complementary metal oxide semiconductor (CMOS) inverter connected to the first terminal, the second terminal, said transistor and said voltage stabilizer, said CMOS inverter interrupting the passing of current between said voltage stabilizer and the second terminal when said transistor is in its off switching state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A noninverting transistor switch having only three terminals, said three terminals being a first terminal, a second terminal and a third terminal, said noninverting transistor switch comprising:
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(a) a first transistor including a drain, a source and a gate, the drain of said first transistor being connected to the third terminal and the source of said first transistor being connected to the second terminal, (b) a second transistor including a drain, a source and a gate, the drain of said second transistor being connected to the third terminal and the gate of said second transistor being connected to the second terminal, (c) a third transistor including a drain, a source and a gate, the drain of said third transistor being connected to the gate of said first transistor, the source of said third transistor being connected to the second terminal and the gate of said third transistor being connected to the first terminal, and (d) a fourth transistor including a drain, a source and a gate, the drain of said fourth transistor being connected to the gate of said first transistor, the source of said fourth transistor being connected to the source of said second transistor and the gate of said fourth transistor being connected to the first terminal. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A noninverting transistor switch having only three terminals, said three terminals being a first terminal, a second terminal and a third terminal, said noninverting transistor switch comprising:
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(a) a first transistor including a drain, a source and a gate, the drain of said first transistor being connected to the third terminal and the source of said first transistor being connected to the second terminal, (b) a second transistor including a drain, a source and a gate, the drain of said second transistor being connected to the third terminal and the gate of said second transistor being connected to the second terminal, (c) a third transistor including a drain, a source and a gate, the drain of said third transistor being connected to the gate of said first transistor, the source of said third transistor being connected to the second terminal and the gate of said third transistor being connected to the source of said second transistor, and (d) a fourth transistor including a drain, a source and a gate, the drain of said fourth transistor being connected to the gate of said first transistor, the source of said fourth transistor being connected to the source of said second transistor and the gate of said fourth transistor being connected to the first terminal.
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19. A noninverting transistor switch having only three terminals, said three terminals being a first terminal, a second terminal and a third terminal, said noninverting transistor switch comprising:
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(a) a first transistor including a drain, a source and a gate, the drain of said first transistor being connected to the third terminal and the source of said first transistor being connected to the second terminal, (b) a second transistor including a drain, a source and a gate, the drain of said second transistor being connected to the third terminal and the gate of said second transistor being connected to the second terminal, (c) a third transistor including a drain, a source and a gate, the drain of said third transistor being connected to the gate of said first transistor, the source of said third transistor being connected to the source of said second transistor and the gate of said third transistor being connected to the first terminal, and (d) a resistor having a first terminal and a second terminal, the first terminal of said resistor being connected to the drain of said third transistor, the second terminal of said resistor being connected to the gate of said second transistor.
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Specification
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Litigation Data
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Current AssigneeOpticurrent, LLC (Longhorn Asset Group LLC)
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Original AssigneeJames S. Congdon
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InventorsCongdon, James S.
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Primary Examiner(s)Tan, Vibol
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Application NumberUS10/466,789Publication NumberTime in Patent Office1,376 DaysField of Search326/81, 326/108, 326119-121, 327/206, 327/427, 327/430, 327/432, 327/483US Class Current326/24CPC Class CodesH03K 17/04123 in field-effect transistor ...H03K 17/687 the devices being field-eff...H03K 2217/0036 Means reducing energy consu...
