Methods and apparatus for packaging integrated circuit devices
DC
First Claim
Patent Images
1. An integrally packaged integrated circuit device comprising:
- an integrated circuit die comprising;
a crystalline substrate having first and second generally planar surfaces and edge surfaces; and
an active surface formed on said first generally planar surface;
at least one chip scale packaging layer formed over said active surface;
at least one gap formed between said crystalline substrate and said at least one chip scale packaging layer; and
at least one electrical contact formed over said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
10 Assignments
Litigations
1 Petition
Accused Products
Abstract
An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
250 Citations
11 Claims
-
1. An integrally packaged integrated circuit device comprising:
an integrated circuit die comprising;
a crystalline substrate having first and second generally planar surfaces and edge surfaces; and
an active surface formed on said first generally planar surface;
at least one chip scale packaging layer formed over said active surface;
at least one gap formed between said crystalline substrate and said at least one chip scale packaging layer; and
at least one electrical contact formed over said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
Litigation Data
-
Current AssigneeInvensas Corporation
-
Original AssigneeShellcase Ltd. (Adeia Inc.)
-
InventorsKatraro, Reuven, Aksenton, Julia, Oganesian, Vage, Zilber, Gil
-
Primary Examiner(s)NGUYEN, CUONG QUANG
-
Application NumberUS10/462,576Publication NumberTime in Patent Office904 DaysField of Search257676-690US Class Current257/678CPC Class CodesH01L 2224/02319 by using a preformH01L 2224/02321 ReworkingH01L 2224/02335 Free-standing redistributio...H01L 2224/0236 Shape of the insulating lay...H01L 2224/024 Material of the insulating ...H01L 2224/0401 Bonding areas specifically ...H01L 2224/13099 MaterialH01L 2224/274 by blanket deposition of th...H01L 23/3114 the device being a chip sca...H01L 24/11 Manufacturing methods for b...H01L 24/12 Structure, shape, material ...H01L 24/13 of an individual bump conne...H01L 24/94 at wafer-level, i.e. with c...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0001 Technical content checked b...H01L 2924/01005 Boron [B]H01L 2924/01006 Carbon [C]H01L 2924/01013 Aluminum [Al]H01L 2924/01022 Titanium [Ti]H01L 2924/01024 Chromium [Cr]View All
