CAM cells and differential sense circuits for content addressable memory (CAM)

DC CAFC

US 6,999,331 B2
Filed: 02/27/2004
Issued: 02/14/2006
Est. Priority Date: 10/04/2001
Status: Expired due to Term

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1. A ternary content addressable memory (TCAM) comprising:

an array of TCAM cells arranged in a plurality of rows and a plurality of columns;

a plurality of match lines, one match line for each row of TCAM cells and operatively coupled to a plurality of output transistors for the TCAM cells in each row;

a plurality of dummy lines, one dummy line for each row of TCAM cells and operatively coupled to a plurality of dummy transistors for the TCAM cells in each row;

a plurality of match data bit lines and their complements, one pair of match data bit line and its complement for each column of TCAM cells to provide a match data and its complement to compare with the content stored in each TCAM cell of that column;

a column of dummy TCAM (DTCAM) cells, each connected to the match line and the dummy line in each row;

a pair of dummy match data bit line and its complement for the column of DTCAM cells to provide a dummy match data and its complement to compare with the content stored in each DTCAM cell;

a sense amplifier connected to the match line and the dummy line in each row; and

current sources connected to each of the match line and the dummy line in each row.

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Abstract

A dummy Content-addressable memory (CAM) cell and a dummy Ternary Content-addressable memory (TCAM) cell are connected to each row in a CAM and a ternary CAM array, respectively, to enable a differential match line sensing based on the content stored. The ternary content-addressable memory (TCAM) cell is for a differential match line sensing in low power applications. A method includes generating a voltage difference between match line signal and a reference line signal, and then detecting and amplifying the voltage difference to determine a match or a mismatch.

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9 Claims

1. A ternary content addressable memory (TCAM) comprising:
- an array of TCAM cells arranged in a plurality of rows and a plurality of columns;
  
  a plurality of match lines, one match line for each row of TCAM cells and operatively coupled to a plurality of output transistors for the TCAM cells in each row;
  
  a plurality of dummy lines, one dummy line for each row of TCAM cells and operatively coupled to a plurality of dummy transistors for the TCAM cells in each row;
  
  a plurality of match data bit lines and their complements, one pair of match data bit line and its complement for each column of TCAM cells to provide a match data and its complement to compare with the content stored in each TCAM cell of that column;
  
  a column of dummy TCAM (DTCAM) cells, each connected to the match line and the dummy line in each row;
  
  a pair of dummy match data bit line and its complement for the column of DTCAM cells to provide a dummy match data and its complement to compare with the content stored in each DTCAM cell;
  
  a sense amplifier connected to the match line and the dummy line in each row; and
  
  current sources connected to each of the match line and the dummy line in each row.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- - 2. The TCAM of claim 1, herein each TCAM cell comprises:
    - a memory cell operable to store a data bit value;
      
      a secondary cell operable t store a control bit value; and
      
      a comparison circuit coupled to the memory cell and the secondary cell and configured to detect the data bit value stored in the memory cell and the control bit value stored in the secondary cell, the comparison circuit including;
      
      a pair of output transistors coupled to the corresponding match line and configured to provide a drive for the match line based on the detected data bit value and the detected control bit value; and
      
      a pair of dummy transistors coupled to the corresponding dummy line to provide a drive for the dummy line based on the detected control bit value, wherein the match line and the dummy line are used to detect an output value provided by the TCAM cell.
  - 3. The TCAM of claim 1, wherein each DTCAM cell comprises:
    - a memory cell operable to store a data bit value;
      
      a secondary cell operable to store a control bit value; and
      
      a comparison circuit coupled to the memory cell and the secondary cell and configured to detect the data bit value stored in the memory cell and the control bit value stored in the secondary cell, the comparison circuit including;
      
      a pair of output transistors coupled to the corresponding match line and configured to provide a drive for the match line based on the detected data bit value and the detected control bit value; and
      
      a pair of dummy transistors coupled to the corresponding dummy line and configured to provide a drive for the dummy line based on the detected inverted data bit value and the detected control bit value.
  - 4. The TCAM of claim 3, wherein the dummy transistors have smaller dimension and less driving ability than the output transistors, are located in close proximity to the output transistors, and are turned ON during sensing operation to enable the comparison of the corresponding row.
  - 5. The TCAM of claim 3, wherein the dummy transistors are turned OFF and the output transistors are turned ON during sensing operation to disable the comparison of the corresponding row.
  - 6. The TCAM of claim 1, wherein the sense amplifier connected to the match line and the dummy line in each row comprises:
    - two inverters connected to each other in a way of positive feedback; and
      
      a P type transistor serially connected to both inverters and Vdd.
  - 7. The TCAM of claim 1, wherein the current sources connected to each of the match line and the dummy line in each row are P type transistors to provide currents from Vdd to the match line and the dummy line.
  - 8. The TCAM of claim 1, wherein the match line and the dummy line in each row are connected to ground through respective N type transistors.

9. A method of detecting a match or a mismatch state of a comparison result in each row of a ternary content addressable memory (TCAM) having an array of TCAM cells arranged in rows and columns, a plurality of match lines and dummy lines, one match line and one dummy line coupled to the TCAM cells in each row, a plurality of match data bit lines and their complements, one pair of match data bit line and its complement coupled to the TCAM cells in each column, a column of dummy TCAM (DTCAM) cells, each coupled to the match line and the dummy line in each row, a pair of dummy match data bit line and its complement coupled to the DTCAM cells, a sense amplifier coupled to the match line and the dummy line in each row, current sources connected between Vdd and each of the match line and the dummy line in each row, and switches connected between ground and each of the match line and the dummy line, the method comprising:
- disabling the current sources such that there is no current flowing from Vdd to the match line and the dummy line;
  
  disabling the sense amplifier;
  
  enabling the switches to establish conducting paths from the match line and the dummy line to ground to make the potential of the match line and the dummy line equal to the ground voltage potential and discharge the match line and the dummy line to ground;
  
  disabling the switch to shut off conducting paths from the match line and the dummy line to ground after the voltage potentials is of both the match line and the dummy line are equal to the ground voltage potential;
  
  sending a plurality of match data and their complements to the TCAM cells through the corresponding match bit lines and their complements to compare with the content stored in the corresponding TCAM cells;
  
  sending a dummy match data and its complement to the DTCAM cell through the dummy match data bit line and its complement to compare with the content stored in the DTCAM cell;
  
  enabling the current sources to establish conducting paths from Vdd to the match line and the dummy line and pull the potential of the match line and the dummy line to a level less than half Vdd;
  
  disabling the current sources to shut off the conducting paths from Vdd to the match line and the dummy line; and
  
  enabling the sense amplifier to sense the voltage difference between the match line and the dummy line and determine the match or the mismatch state, finishing one comparison cycle.

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Current Assignee
Xiaohua Huang
Original Assignee
Xiaohua Huang
Inventors
Huang, Xiaohua
Primary Examiner(s)
Phung, Anh
Assistant Examiner(s)
HUR, JUNG H

Application Number

US10/789,661
Publication Number

US 20040228156A1
Time in Patent Office

718 Days
Field of Search

365/49, 365/207, 365/210, 711/108
US Class Current

365/49.17
CPC Class Codes

G11C 15/04 using semiconductor elements

CAM cells and differential sense circuits for content addressable memory (CAM)

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CAM cells and differential sense circuits for content addressable memory (CAM)

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