Solid state imaging device with semiconductor imaging and processing chips
DC
First Claim
Patent Images
1. A solid state imaging device comprising:
- an imaging semiconductor chip for outputting an analog image signal in which all transistors are formed of the same conductivity type; and
an image processing semiconductor chip, to which the analog image signal is input, comprising CMOS transistors,wherein the imaging semiconductor chip comprises;
a photoelectric converter for converting light into an electric signal; and
an amplifier for amplifying the electric signal generated by the photoelectric converter, andwherein the image processing semiconductor chip comprises;
an AD converter for converting the analog image signal output from the imaging semiconductor ship into a digital signal; and
an image processing circuit for performing image processing based on the digital signal converted by the AD converter.
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Abstract
The present invention provides a small, high-performance imaging device and its application to products at low cost by preventing noise superimposed on a timing pulse feed line from affecting the output of an imaging chip. The imaging device includes two chips: an imaging chip 101 including a sensor 102 and an image processing chip 106 including an image processing circuit 110. The transistors of all circuits in the imaging chip 101 are formed as either nMOS or pMOS transistors. The imaging chip 101 is stacked on the image processing chip 106.
63 Citations
14 Claims
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1. A solid state imaging device comprising:
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an imaging semiconductor chip for outputting an analog image signal in which all transistors are formed of the same conductivity type; and an image processing semiconductor chip, to which the analog image signal is input, comprising CMOS transistors, wherein the imaging semiconductor chip comprises; a photoelectric converter for converting light into an electric signal; and an amplifier for amplifying the electric signal generated by the photoelectric converter, and wherein the image processing semiconductor chip comprises; an AD converter for converting the analog image signal output from the imaging semiconductor ship into a digital signal; and an image processing circuit for performing image processing based on the digital signal converted by the AD converter.
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2. The solid state imaging device according to claim 1, wherein the imaging semiconductor chip is stacked on the image processing semiconductor chip.
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3. The solid state imaging device according to claim 1, wherein all transistors of the imaging semiconductor chip are formed as n-channel MOS transistors.
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4. The solid state imaging device according to claim 1, wherein all transistors of the imaging semiconductor chip are formed as p-channel MOS transistors.
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5. The solid state imaging device according to claim 1, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected electrically by a bonding wire.
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6. The solid state imaging device according to claim 1, wherein a through electrode is provided in the imaging semiconductor chip, and the imaging semiconductor chip and the image processing semiconductor chip are connected electrically via wiring connected to the through electrode.
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7. The solid state imaging device according to claim 6, wherein the through electrode is a Si through electrode.
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8. The solid state imaging device according to claim 1, wherein the image processing semiconductor chip comprises:
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a timing generator for supplying a timing pulse to the imaging semiconductor chip; a gain control amplifier; and an analog/digital converter.
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9. The solid state imaging device according to claim 2, wherein the image processing semiconductor chip comprises a plurality of terminals including a timing pulse output terminal for outputting a timing pulse,
the imaging semiconductor chip comprises a plurality of terminals including a timing pulse input terminal for receiving the timing pulse, and the imaging semiconductor chip is stacked on the image processing semiconductor chip so that the timing pulse input terminal and the timing pulse output terminal are located close to each other.
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10. The solid state imaging device according to claim 2, wherein the imaging semiconductor chip comprises a plurality of terminals including the image signal output terminal for outputting an image signal,
the image processing semiconductor chip comprises a plurality of terminals including an image signal input terminal for receiving the image signal, and the imaging semiconductor chip is stacked on the image processing semiconductor chip so that the image signal output terminal and the image signal input terminal are located close to each other.
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11. Equipment comprising:
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the solid state imaging device according to claim 1; and an image processing portion for processing a static image or a dynamic image produced by the solid state imaging device.
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12. The equipment according to claim 11, further comprising:
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a voice coder for encoding and compressing speech data; and a communication controller for modulating the compressed speech data for communications, wherein the equipment is a cellular phone.
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13. The equipment according to claim 11, further comprising:
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a voice coder for encoding and compressing speech data; and a communication controller for modulating the compressed speech data for communications, wherein the equipment is an information terminal.
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14. The equipment according to claim 11, further comprising:
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an image coder/decoder for compressing and expanding images; a recording medium controller for recording compressed image data on a recording medium; and a display controller for displaying the images, wherein the equipment is a digital still camera.
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Specification
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Litigation Data
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsInokuma, Kazuyuki, Fujii, Toshiya, Yamaguchi, Takumi, Kasuga, Shigetaka
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Primary Examiner(s)Luu, Thanh X.
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Application NumberUS10/676,136Publication NumberTime in Patent Office1,204 DaysField of Search250/208.1, 250/239, 257/686, 348/222.1US Class Current250/208.1CPC Class CodesH01L 2224/13025 the bump connector being di...H01L 2224/16145 the bodies being stackedH01L 2224/16227 the bump connector connecti...H01L 2224/32145 the bodies being stackedH01L 2224/32225 the item being non-metallic...H01L 2224/48145 the bodies being stackedH01L 2224/48227 connecting the wire to a bo...H01L 2224/73265 Layer and wire connectorsH01L 2924/00 Indexing scheme for arrange...H01L 2924/00012 Relevant to the scope of th...H04N 23/54 Mounting of pick-up tubes, ...
