Memory controller useable in a data processing system
DC CAFCFirst Claim
1. A data processing system, comprising:
- a system bus;
a system bus master, coupled to the system bus;
a first memory controller for controlling a first memory;
a second memory controller for controlling a second memory; and
a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller, wherein;
the second memory controller comprises arbitration logic for arbitrating between the system bus master and the first memory controller for access to the second memory;
when the data is transferred from the first memory controller to the second memory controller, the data is received by the first memory controller from the storage locations within the first memory prior to transferring the data to the second memory controller, andwhen the data is transferred from the second memory controller to the first memory controller, the data is received by the second memory controller from storage locations within the second memory prior to transferring the data to the first memory controller.
19 Assignments
Litigations
2 Petitions
Accused Products
Abstract
One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes a system bus, a system bus master coupled to the system bus, a first memory controller for controlling a first memory, a second memory controller for controlling a second memory, and a memory controller bus operating independent of the system bus to transfer data between the first memory controller and the second memory controller. The memory controller bus may include a data bus and read, write, and acknowledge signals. In one embodiment, the first memory is a block accessible memory such as a NAND Flash memory and the second memory is a random access memory (RAM) such as an SDRAM. The second memory may include arbitration logic for arbitrating between the system bus master and the first memory controller.
35 Citations
19 Claims
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1. A data processing system, comprising:
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a system bus; a system bus master, coupled to the system bus; a first memory controller for controlling a first memory; a second memory controller for controlling a second memory; and a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller, wherein; the second memory controller comprises arbitration logic for arbitrating between the system bus master and the first memory controller for access to the second memory; when the data is transferred from the first memory controller to the second memory controller, the data is received by the first memory controller from the storage locations within the first memory prior to transferring the data to the second memory controller, and when the data is transferred from the second memory controller to the first memory controller, the data is received by the second memory controller from storage locations within the second memory prior to transferring the data to the first memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A data processing system, comprising:
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a system bus; a system bus master, coupled to the system bus; a first memory controller, coupled to the system bus, for controlling a first memory; a second memory controller, coupled to the system bus, for controlling a second memory; arbitration logic, coupled to the second memory controller, said arbitration logic arbitrating between the system bus master and the first memory controller for access to the second memory; and a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller. - View Dependent Claims (16, 17, 18)
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19. A data processing system, comprising:
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a system bus; a processor, coupled to the system bus; direct memory access (DMA) circuitry coupled to the system bus; system bus arbitration logic, coupled to the system bus, said system bus arbitration logic performing arbitration on the system bus; a first memory controller for controlling a first memory; a second memory controller for controlling a second memory; a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory and second memory by way of the first memory controller and the second memory controller; and memory controller bus arbitration logic, coupled to the second memory controller, said arbitration logic performing arbitration between the system bus master and the first memory controller for access to the second memory.
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Specification