Smart lock-in circuit for phase-locked loops
DC
First Claim
1. A smart lock-in circuit for enabling any phase-locked loop including at least a filter to become locked according to schedule, comprising:
- a feedback line connected to an output and input of the smart lock-in circuit and also coupled to an output of a filter;
a sensor for sensing a voltage at the filter output, comparing with a midpoint voltage decided by device aspect ratios of the sensor, and providing its response;
two stacked PMOS transistors connected between power supply and the output; and
two stacked NMOS transistors connected between the output and ground.
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Abstract
The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.
7 Citations
19 Claims
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1. A smart lock-in circuit for enabling any phase-locked loop including at least a filter to become locked according to schedule, comprising:
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a feedback line connected to an output and input of the smart lock-in circuit and also coupled to an output of a filter; a sensor for sensing a voltage at the filter output, comparing with a midpoint voltage decided by device aspect ratios of the sensor, and providing its response; two stacked PMOS transistors connected between power supply and the output; and two stacked NMOS transistors connected between the output and ground. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification
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- Resources
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Current AssigneeSmart Semiconductor, LLC (Equitable IP Corporation)
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Original AssigneeANA Semiconductor
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InventorsPark, Sangbeom
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Primary Examiner(s)Pascal, Robert
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Assistant Examiner(s)Gannon, Levi
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Application NumberUS11/036,837Publication NumberTime in Patent Office864 DaysField of Search331/57, 331/DIG.2, 331/17, 331/16US Class Current331/16CPC Class CodesH03L 7/0891 the up-down pulses controll...H03L 7/10 for assuring initial synchr...H03L 7/101 using an additional control...H03L 7/105 Resetting the controlled os...Y10S 331/02 Phase locked loop having lo...
