Semiconductor device and method for fabricating the same
DC
First Claim
1. A semiconductor device comprising:
- a substrate provided with a semiconductor element;
a first interlayer dielectric film provided on the substrate;
a first interconnect groove provided in the first interlayer dielectric film;
a first interconnect provided within the first interconnect groove and having convex or concave portions at least at one of its side surfaces and bottom surface;
a second interlayer dielectric film provided over the first interlayer dielectric film and the first interconnect; and
a first plug that passes through the second interlayer dielectric film and comes into contact with a part of the first interconnect.
3 Assignments
Litigations
2 Petitions
Accused Products
Abstract
An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.
12 Citations
21 Claims
-
1. A semiconductor device comprising:
-
a substrate provided with a semiconductor element; a first interlayer dielectric film provided on the substrate; a first interconnect groove provided in the first interlayer dielectric film; a first interconnect provided within the first interconnect groove and having convex or concave portions at least at one of its side surfaces and bottom surface; a second interlayer dielectric film provided over the first interlayer dielectric film and the first interconnect; and a first plug that passes through the second interlayer dielectric film and comes into contact with a part of the first interconnect. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A method for fabricating a semiconductor device, the method comprising the steps of:
-
a) forming a first interlayer dielectric film on a substrate provided with a semiconductor element; b) forming, in the first interlayer dielectric film, an interconnect groove having concave or convex portions at its bottom surface; c) filling the interconnect groove with a conductor material, thereby forming an interconnect with convex or concave portions having shapes corresponding to those of the concave or convex portions of the interconnect groove; d) forming a second interlayer dielectric film over the first interlayer dielectric film and the interconnect; and e) forming a plug that passes through the second interlayer dielectric film and comes into contact with a part of the interconnect. - View Dependent Claims (19, 20, 21)
-
Specification
-
- Resources
-
Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
-
Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
-
InventorsUmimoto, Hiroyuki, Ueda, Tetsuya, Handa, Takato
-
Primary Examiner(s)Sarkar; Asok K.
-
Assistant Examiner(s)Yevsikov; Victor V.
-
Application NumberUS10/900,272Publication NumberTime in Patent Office1,133 DaysField of Search257/774, 257/767, 257/758.741US Class Current257/774CPC Class CodesH01L 21/76801 characterised by the format...H01L 21/76816 Aspects relating to the lay...H01L 21/76832 Multiple layersH01L 21/76834 formation of thin insulatin...H01L 21/76843 formed in openings in a die...H01L 21/76865 Selective removal of parts ...H01L 21/76877 Filling of holes, grooves o...H01L 21/76886 Modifying permanently or te...H01L 23/5283 Cross-sectional geometryH01L 23/53238 Additional layers associate...H01L 23/53295 Stacked insulating layersH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
