Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
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First Claim
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1. An instruction-processing system with minimal static power leakage, the instruction-processing system comprising:
- a core with instruction-processing circuitry;
an area coupled to the core;
a core voltage provided to the core; and
an area voltage provided to the area;
wherein in a normal operation mode;
a clock signal to the core is active;
the core voltage is a first value;
the core is active;
the area voltage is a second value; and
the area is active;
wherein in a first power-saving mode that is exited upon receipt of an interrupt signal;
the clock signal to the core is inactive;
the core voltage is equal to or greater than the first value; and
the area voltage is equal to or greater than the second value;
wherein in a second power-saving mode that can be exited upon receipt of a signal that is not an interrupt signal;
the clock signal to the core is inactive;
the core voltage is less than the first value; and
the area voltage is equal to or greater than the second value.
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Reexamination
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Abstract
One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.
15 Citations
21 Claims
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1. An instruction-processing system with minimal static power leakage, the instruction-processing system comprising:
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a core with instruction-processing circuitry; an area coupled to the core; a core voltage provided to the core; and an area voltage provided to the area; wherein in a normal operation mode; a clock signal to the core is active; the core voltage is a first value; the core is active; the area voltage is a second value; and the area is active; wherein in a first power-saving mode that is exited upon receipt of an interrupt signal; the clock signal to the core is inactive; the core voltage is equal to or greater than the first value; and the area voltage is equal to or greater than the second value; wherein in a second power-saving mode that can be exited upon receipt of a signal that is not an interrupt signal; the clock signal to the core is inactive; the core voltage is less than the first value; and the area voltage is equal to or greater than the second value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for minimizing static power leakage in an instruction-processing system, wherein the instruction-processing system comprises a core with instruction-processing circuitry, an area coupled to the core, a core voltage provided to the core, and an area voltage provided to the area, the method comprising:
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entering a normal operation mode by; providing a clock signal to the core; providing the core with a core voltage that is equal to a first value; providing the area with an area voltage that is equal to a second value; entering a first power-saving mode by; disabling the clock signal to the core; providing the core with a core voltage that is equal to or greater than the first value; and providing the area with an area voltage that is equal to or greater than the second value; exiting the first power-saving mode upon receipt of an interrupt signal; entering a second power-saving mode by; disabling the clock signal to the core; setting the core voltage to a value less than the first value; and providing the area with an area voltage that is equal to or greater than the second value; and exiting the second power-saving mode upon receipt of a signal that is not an interrupt signal. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer-readable medium containing data representing an instruction-processing system with minimal static power leakage, the instruction- processing system comprising:
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a core with instruction-processing circuitry; an area coupled to the core; a core voltage provided to the core; and an area voltage provided to the area; wherein in a normal operation mode; a clock signal to the core is active; the core voltage is a first value; the core is active; the area voltage is a second value; and the area is active; wherein in a first power-saving mode that is exited upon receipt of an interrupt signal; the clock signal to the core is inactive; the core voltage is equal to or greater than the first value; and the area voltage is equal to or greater than the second value; wherein in a second power-saving mode that can be exited upon receipt of a signal that is not an interrupt signal; the clock signal to the core is inactive; the core voltage is less than the first value; and the area voltage is equal to or greater than the second value. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification
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Litigation Data
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Current AssigneeApple Inc.
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Original AssigneeApple Inc.
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InventorsYoungs, Lynn R.
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Primary Examiner(s)Perveen; Rehana
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Assistant Examiner(s)Stoynov; Stefan
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Application NumberUS11/213,215Publication NumberTime in Patent Office1,013 DaysField of Search713/300US Class Current713/300CPC Class CodesG06F 1/3203 Power management, i.e. even...G06F 1/3228 Monitoring task completion,...G06F 1/3275 Power saving in memory, e.g...G06F 1/3287 by switching off individual...G06F 1/3296 by lowering the supply or o...Y02D 10/00 Energy efficient computing,...Y02D 30/50 in wire-line communication ...
