Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller
DCFirst Claim
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1. A memory accessing method comprising:
- (1) executing a first instruction by a first processor, the first instruction specifying an address of a memory location and an operation to be performed on the memory location;
wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed;
wherein the first processor executes the first instruction without performing the operation and without accessing the memory location;
(2) performing the operation by the co-processor;
wherein the memory location is in a memory and the first processor executes the first instruction without accessing the memory;
the first processor sends the information to the co-processor via a first interface directly connected to the first processor and the co-processor but not to the memory; and
performing the operation by the co-processor comprises the co-processor accessing the memory via a second interface directly connected to the co-processor and the memory but not to the first processor.
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Abstract
This disclosure relates to communications among processors, coprocessors and memory. Specifically, a method and apparatus provide a single-cycle instruction (“store-and-load”) that stores a command to a co-processor to atomically process data and that loads resultant processed data.
22 Citations
64 Claims
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1. A memory accessing method comprising:
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(1) executing a first instruction by a first processor, the first instruction specifying an address of a memory location and an operation to be performed on the memory location; wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed; wherein the first processor executes the first instruction without performing the operation and without accessing the memory location; (2) performing the operation by the co-processor; wherein the memory location is in a memory and the first processor executes the first instruction without accessing the memory; the first processor sends the information to the co-processor via a first interface directly connected to the first processor and the co-processor but not to the memory; and performing the operation by the co-processor comprises the co-processor accessing the memory via a second interface directly connected to the co-processor and the memory but not to the first processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory accessing method comprising:
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(1) executing a first instruction by a first processor, the first instruction specifying an address of a memory location and an operation to be performed on the memory location; wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed; wherein the first processor executes the first instruction without performing the operation and without accessing the memory location; (2) performing the operation by the co-processor; wherein the first processor executes a plurality of tasks, executing the first instruction comprises the first processor specifying to the co-processor a task executing the first instruction, and performing the operation by the co-processor comprises the co-processor specifying the task to the first processor. - View Dependent Claims (20, 21)
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22. A memory accessing method comprising:
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(1) executing a first instruction by a first processor, the first instruction specifying an address of a memory location and an operation to be performed on the memory location; wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed; wherein the first processor executes the first instruction without performing the operation and without accessing the memory location; (2) performing the operation by the co-processor; wherein the first instruction is one of a plurality of first instructions executed by one or more processors comprising the first processor, each first instruction specifying an address of an associated memory location and an associated operation to be performed on the associated memory location; wherein the execution of each of the first instructions comprises the one or more processors sending associated information to the co-processor, the associate information specifying to the co-processor the associated address and the associated operation; wherein the one or more processors execute the first instructions without performing the associated operations and without accessing the associated memory locations; wherein the associated operations are performed by the co-processor; wherein one or more of the first instructions are each associated with a sequence number, and the one or more of the first instructions each specify whether sequencing is enabled or disabled; wherein if the sequencing is disabled, the co-processor performs the associated operations in an order in which the co-processor receives the first instructions; wherein if the sequencing is enabled, the co-processor performs each associated operation only when a current sequence number maintained by the co-processor becomes equal to the sequence number associated with the first instruction associated with the operation.
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23. An apparatus comprising a first processor for executing computer instructions, the first processor comprising circuitry for executing a first instruction, the first instruction specifying an address of a memory location and an operation to be performed on the memory location;
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wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed; wherein the first processor executes the first instruction without performing the operation and without accessing the memory location; the apparatus further comprising the co-processor, the memory, a first interface directly connected to the first processor and the co-processor but not to the memory, and a second interface directly connected to the co-processor and the memory but not to the first processor, wherein; the first processor sends the information to the co-processor via the first interface; and performing the operation by the co-processor comprises the co-processor accessing the memory via the second interface. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A first processor for executing computer instructions, the first processor comprising circuitry for executing a first instruction, the first instruction specifying an address of a memory location and an operation to be performed on the memory location;
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wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed; wherein the first processor executes the first instruction without performing the operation and without accessing the memory location; wherein the first processor is to execute a plurality of tasks, executing the first instruction comprises the first processor specifying to the co-processor a task executing the first instruction, and the operation comprises the co-processor specifying the task to the first processor. - View Dependent Claims (42, 43)
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44. A first processor for executing computer instructions, the first processor comprising circuitry for executing a first instruction, the first instruction specifying an address of a memory location and an operation to be performed on the memory location;
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wherein executing the first instruction comprises the first processor sending information to a co-processor, the information specifying the address of the memory location and the operation to be performed; wherein the first processor executes the first instruction without performing the operation and without accessing the memory location; wherein the first processor is operable to operate with the first instruction being one of a plurality of first instructions to be executed by one or more processors comprising the first processor, each first instruction specifying an address of an associated memory location and an associated operation to be performed on the associated memory location; wherein the execution of each of the first instructions comprises the one or more processors sending associated information to the co-processor, the associate information specifying to the co-processor the associated address and the associated operation; wherein the one or more processors execute the first instructions without performing the associated operations and without accessing the associated memory locations; wherein the associated operations are performed by the co-processor; wherein one or more of the first instructions are each associated with a sequence number, and the one or more of the first instructions each specify whether sequencing is enabled or disabled; wherein if the sequencing is disabled, the co-processor performs the associated operations in an order in which the co-processor receives the first instructions; wherein if the sequencing is enabled, the co-processor performs each associated operation only when a current sequence number maintained by the co-processor becomes equal to the sequence number associated with the first instruction associated with the operation.
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45. A semaphore handling method comprising:
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(1) executing a first instruction by a processor, the first instruction specifying a semaphore operation to be performed by a co-processor, the semaphore operation being (i) a get-semaphore operation to acquire a semaphore by the processor, or (ii) a release-semaphore operation to release a semaphore by the processor; wherein the execution of the first instruction comprises the processor sending information to the co-processor, the information specifying the semaphore operation; wherein the processor executes the first instruction without performing the semaphore operation; (2) performing the semaphore operation by the co-processor. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54)
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55. A processor for executing computer instructions, the processor comprising circuitry for executing a first instruction, the first instruction specifying a semaphore operation to be performed by a co-processor, the semaphore operation being (i) a get-semaphore operation to acquire a semaphore by the processor, or (ii) a release-semaphore operation to release a semaphore by the processor;
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wherein the execution of the first instruction comprises the processor sending information to the co-processor, the information specifying the semaphore operation; wherein the processor executes the first instruction without performing the semaphore operation. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63, 64)
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Specification