Filter-based lock-in circuits for PLL and fast system startup

US 7,515,003 B2
Filed: 05/30/2007
Issued: 04/07/2009
Est. Priority Date: 05/30/2007
Status: Expired due to Fees

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1. A filter-based lock-in circuit used in a system for reducing system startup time and system latency time, comprising:

an upper transistor and a lower transistor connected in series between a power supply and ground having a shared terminal which becomes a single bidirectional node, wherein the shared terminal is defined by a junction between the upper transistor and the lower transistor;

a sensing inverter for sensing a voltage at the single bidirectional node and comparing it with an input transition voltage of the sensing inverter which causes an output of the sensing inverter to be centered at half the power supply voltage wherein an input terminal of the sensing inverter is connected to the single bidirectional node;

a logic gate coupled between an output terminal of the sensing inverter and a gate terminal of the upper transistor; and

wherein an initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter.

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Abstract

All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower transistor have a shared source (or drain) terminal which becomes a single bidirectional node. They further comprise a sensing gate and a logic gate. The sensing inverter has a function of sensing a voltage at the single bidirectional node and comparing it with an input transition voltage since an input terminal of the sensing inverter is connected to the single bidirectional node. An initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter, where the input transition voltage is an input voltage which causes an output voltage to be

$\frac{V_{DD}}{2} .$
Consequently, all embodiments of the present invention provide a fast lock-in time performance and achieve a drastic improvement in system startup time, system latency time, system simulation time, system test time, cost, and time to market

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1. A filter-based lock-in circuit used in a system for reducing system startup time and system latency time, comprising:
- an upper transistor and a lower transistor connected in series between a power supply and ground having a shared terminal which becomes a single bidirectional node, wherein the shared terminal is defined by a junction between the upper transistor and the lower transistor;
  
  a sensing inverter for sensing a voltage at the single bidirectional node and comparing it with an input transition voltage of the sensing inverter which causes an output of the sensing inverter to be centered at half the power supply voltage wherein an input terminal of the sensing inverter is connected to the single bidirectional node;
  
  a logic gate coupled between an output terminal of the sensing inverter and a gate terminal of the upper transistor; and
  
  wherein an initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
- - 2. The circuit as recited in claim 1 wherein the upper transistor and the lower transistor are a PMOS transistor and an NMOS transistor, respectively, the shared terminal is a drain terminal that the PMOS transistor and the NMOS transistor have, and the logic gate comprises an odd number of inverters, wherein the NMOS transistor has a gate terminal which is connected to ground.
  - 3. The circuit as recited in claim 1 wherein the upper transistor and the lower transistor are a PMOS transistor and an NMOS transistor, respectively, the shared terminal is a drain terminal that the PMOS transistor and the NMOS transistor have, and the logic gate comprises a two-input NAND gate, which is used as an enabling inverter with one input voltage inverted from a power-down pin voltage and the other input terminal coupled to the output terminal of the sensing inverter, wherein the NMOS transistor has a gate terminal which is connected to a power-down pin and is at ground during normal mode.
  - 4. The circuit as recited in claim 1 wherein the upper transistor and the lower transistor are an NMOS transistor and a PMOS transistor, respectively, the shared terminal is a source terminal that the NMOS transistor and the PMOS transistor have, and the logic gate comprises an even number of inverters, wherein the PMOS transistor has a gate terminal which is connected to the power supply.
  - 5. The circuit as recited in claim 1 wherein the upper transistor and the lower transistor are an NMOS transistor and a PMOS transistor, respectively, the shared terminal is a source terminal that the NMOS transistor and the PMOS transistor have, and the logic gate comprises a combination of an inverter and a two-input NOR gate, wherein the NOR gate is used as an enabling inverter with one input voltage serving as a power-down pin voltage and the other input voltage inverted from the output voltage of the sensing inverter, wherein the PMOS transistor has a gate terminal which is inverted from the power-down pin and is at the power supply during normal mode.
  - 6. The circuit as recited in claim 1 wherein the single bidirectional node of the filter-based lock-in circuit is also connected to a terminal, which is defined by a junction between a resistor and capacitor in a low-pass filter of a phase-locked loop.
  - 7. The circuit as recited in claim 1 wherein the filter-based lock-in circuit is developed for use in simulating a complete system quickly, realistically, and accurately which incorporates all design components including at least a phase-locked loop before tape-out.
  - 8. The circuit as recited in claim 1 wherein the system is a communication system.
  - 9. The circuit as recited in claim 1 wherein the system is a computer system.
  - 10. The circuit as recited in claim 1 wherein the system is a computer peripheral system.
  - 11. The circuit as recited in claim 1 wherein the system is a consumer electronics system.
  - 12. The circuit as recited in claim 1 wherein the system is an automotive system.
  - 13. The circuit as recited in claim 1 wherein the system is an industrial system.
  - 14. The circuit as recited in claim 1 wherein the system is an instrumentation system.
  - 15. The circuit as recited in claim 1 wherein the system is a cellular phone system.
  - 16. The circuit as recited in claim 1 wherein the system is a digital signal processor system.
  - 17. The circuit as recited in claim 1 wherein the system is a central process unit system.
  - 18. The circuit as recited in claim 1 wherein the system is a clock distribution system.
  - 19. The circuit as recited in claim 1 wherein the system is a memory system.
  - 20. The circuit as recited in claim 1 wherein the filter-based lock-in circuit is developed for use in all types of systems containing at least a phase-locked loop without regard to architecture and topology.

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Current Assignee
Smart Semiconductor, LLC (Equitable IP Corporation)
Original Assignee
ANA Semiconductor
Inventors
Park, Sangbeom
Primary Examiner(s)
KINKEAD, ARNOLD M

Application Number

US11/809,041
Publication Number

US 20080297263A1
Time in Patent Office

678 Days
Field of Search

331/16, 331/17, 331/34, 331/177.R, 327/141, 327/153, 327/161
US Class Current

331/16
CPC Class Codes

H03L 7/0891   the up-down pulses controll...

H03L 7/093   using special filtering or ...

H03L 7/1075   by changing characteristics...

H03L 7/18   using a frequency divider o...

Filter-based lock-in circuits for PLL and fast system startup

First Claim

7 Assignments

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Abstract

9 Citations

20 Claims

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Filter-based lock-in circuits for PLL and fast system startup

First Claim

7 Assignments

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Accused Products

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Abstract

9 Citations

20 Claims

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