Electronic system and method for selectively allowing access to a shared memory
DC
First Claim
Patent Images
1. An electronic system comprising:
- a bus;
a main memory coupled to the bus having stored therein data corresponding to video images;
a video circuit coupled to the bus, the video circuit configured to receive data from the main memory corresponding to a current video image to be decoded and to output decoded video data corresponding to the current video image to be displayed on a display device, the current video image to be displayed adapted to be stored in the main memory;
a processor coupled to the main memory, the processor for storing non-image data in the main memory and retrieving non-image data from the main memory; and
an arbiter circuit coupled to the processor and to the video circuit, the arbiter circuit configured to receive requests for access to the main memory from the video circuit and the processor and to control access to the main memory by;
providing access to the main memory for a request for access to the main memory when the arbiter circuit is in an idle state;
queuing a request for access to the main memory when the arbiter circuit is in a busy state; and
queuing a request for access to the main memory in an order based on a priority of the request and a priority of each of one or more other requests for access to the main memory that are currently queued when the arbiter circuit is in a queue state.
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Accused Products
Abstract
An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
42 Citations
17 Claims
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1. An electronic system comprising:
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a bus; a main memory coupled to the bus having stored therein data corresponding to video images; a video circuit coupled to the bus, the video circuit configured to receive data from the main memory corresponding to a current video image to be decoded and to output decoded video data corresponding to the current video image to be displayed on a display device, the current video image to be displayed adapted to be stored in the main memory; a processor coupled to the main memory, the processor for storing non-image data in the main memory and retrieving non-image data from the main memory; and an arbiter circuit coupled to the processor and to the video circuit, the arbiter circuit configured to receive requests for access to the main memory from the video circuit and the processor and to control access to the main memory by; providing access to the main memory for a request for access to the main memory when the arbiter circuit is in an idle state; queuing a request for access to the main memory when the arbiter circuit is in a busy state; and queuing a request for access to the main memory in an order based on a priority of the request and a priority of each of one or more other requests for access to the main memory that are currently queued when the arbiter circuit is in a queue state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An electronic circuit for use with a memory, comprising:
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a bus coupleable to a memory; a decoder coupled to the bus for receiving encoded video images and for outputting data for displaying decoded video images on a display device, the decoder configured to receive data from the memory corresponding to at least one previously decoded image and to a current image to be decoded and outputting decoded data corresponding to a current image to be displayed, the current image being output for storing in the memory, the decoder having a memory interface circuit; a central processing unit coupled to the bus for accessing the memory, the central processing unit having a memory interface circuit; and an arbiter included in the memory interface circuit of the decoder and coupled to the memory interface circuit of the central processing unit, the arbiter configured to control access to the memory by determining a priority for requests to access the memory, each of the requests received from one of the decoder and the central processing unit, and providing access to the memory based on the determined priorities of the requests. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method, comprising:
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storing in a shared memory data corresponding to video images and other data that does not correspond to video images; receiving in a video decoder data corresponding to a compressed current video image and data corresponding to at least one previously decoded video image from the shared memory, and outputting from the video decoder decoded video data corresponding to the compressed current video image; and for each of multiple requests for access to the shared memory received from the video decoder and one or more other devices, providing access to the shared memory for the request when the shared memory is not being accessed and no other requests to access the shared memory are currently pending; queuing the request when the shared memory is being accessed; and queuing the request in an order based on a priority of the request and a priority of each of one or more other requests that are currently pending when the shared memory is being accessed and the one or more other requests are currently pending. - View Dependent Claims (14, 15, 16, 17)
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Specification
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Litigation Data
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Current AssigneeParthenon Unified Memory Architecture LLC (Acacia Research Corporation)
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Original AssigneeSTMicroelectronics Incorporated (STMicroelectronics NV)
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InventorsOwen, Jefferson Eugene, Colavin, Osvaldo, Diaz, Raul Zegers
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Primary Examiner(s)Nguyen, Hau H
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Application NumberUS12/424,389Publication NumberTime in Patent Office489 DaysField of Search345/541, 345/531, 345/542, 345/547, 345/555, 345/501, 345/519, 345/545US Class Current345/541CPC Class CodesG06F 13/1605 based on arbitration arbitr...G06F 13/18 based on priority control G...G06F 15/167 using a common memory, e.g....G06T 1/60 Memory managementG09G 2340/02 Handling of images in compr...G09G 2360/18 Use of a frame buffer in a ...G09G 5/001 Arbitration of resources in...G09G 5/363 Graphics controllersH04N 19/423 characterised by memory arr...H04N 19/427 Display on the fly, e.g. si...H04N 19/61 in combination with predict...H04N 21/443 OS processes, e.g. booting ...H04N 21/4435 Memory management allocatio...
