Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

DC CAFC

US 7,779,323 B2
Filed: 08/20/2008
Issued: 08/17/2010
Est. Priority Date: 02/15/2001
Status: Expired due to Fees

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First Claim

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1. An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>

1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses;

said apparatus comprising;

(a) means for generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation;

(b) means for applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and

(c) means for analyzing output responses of all said scan cells to locate any faults therein.

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Abstract

A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

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21 Claims

1. An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>
- 1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses;
  
  said apparatus comprising;
  
  (a) means for generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation;
  
  (b) means for applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and
  
  (c) means for analyzing output responses of all said scan cells to locate any faults therein.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
- - 2. The apparatus of claim 1 wherein all said capture clocks are supplied to said clock domains in a way to reduce power consumption during said self-test or scan-test mode.
  - 3. The apparatus of claim 1, wherein said capture clock is programmable to contain said selected number of capture clock pulses, in accordance with said ordered sequence of capture clock pulses, for performing said capture operation on all said scan cells within a selected clock domain controlled by said capture clock;
    - wherein all said capture clock pulses in said capture clock are selectively generated internally or controlled externally, and can be selectively operated at their rated clock speed (at-speed) or at a selected clock speed.
  - 4. The apparatus of claim 3 further comprising means for providing N scan enable (SE) signals each controlling a selected clock domain;
    - wherein all said scan enable (SE) signals are used to switch operations from shift-in to capture, and vice versa; and
      
      wherein each said scan enable (SE) signal is selectively generated internally or controlled externally, and can be selectively operated at its rated clock speed or at a selected clock speed.
  - 5. The apparatus of claim 3, wherein said means for providing N scan enable (SE) signals further comprises means for using one global scan enable (GSE) signal to drive all said scan enable (SE) signals so that said global scan enable (GSE) signal and all said scan enable (SE) signals can be operated at a selected reduced clock speed.
  - 6. The apparatus of claim 1, wherein there are provided shift clock pulses and said means for generating and shifting-in N test stimuli further comprises means for operating all said shift clock pulses at selected clock speeds or at the same clock speed;
    - wherein all said shift clock pulses are selectively skewed so that at any given time only one or more said scan cells are changing states to reduce power consumption.
  - 7. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for applying said capture clock pulses concurrently to two or more selected clock domains which do not interact with each other or do not have any logic block crossing each other, for detecting or locating said faults in said selected clock domains.
  - 8. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for applying a reversed ordered sequence of capture clock pulses from said ordered sequence of capture clock pulses, for detecting or locating additional faults in said integrated circuit or circuit assembly.
  - 9. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively applying a shortened or expanded ordered sequence of capture clock pulses from said ordered sequence of capture clock pulses, for detecting or locating additional faults in said integrated circuit or circuit assembly.
  - 10. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for disabling all capture clock pulses in one or more capture clocks, to facilitate fault diagnosis.
  - 11. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively operating all said capture clock pulses controlling a selected clock domain at a selected clock speed, for detecting or locating stuck-at faults within said selected clock domain.
  - 12. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively operating all said capture clock pulses controlling a selected clock domain at their rated clock speed, for detecting or locating delay faults within said selected clock domain.
  - 13. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively reducing the speed of all said capture clock pulses controlling a selected clock domain to the level, where delay faults associated with all multiple-cycle paths of equal cycle latency within said selected clock domain are detected or located at a predetermined rated clock speed.
  - 14. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively operating all said capture clock pulses controlling two selected clock domains at selected clock speeds, for detecting or locating stuck-at faults crossing said two selected clock domains.
  - 15. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively adjusting the relative clock delay of two said capture clock pulses controlling two selected clock domains, for detecting or locating delay faults crossing said two selected clock domains.
  - 16. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for selectively adjusting the relative clock delay of two said capture clock pulses controlling two selected clock domains to the level, where delay faults associated with all multiple-cycle paths of equal cycle latency crossing said two selected clock domains are detected or located at a predetermined rated clock speed.
  - 17. The apparatus of claim 1, wherein said means for applying an ordered sequence of capture clock pulses further comprises means for controlling the relative clock delay between any two adjacent capture clock pulses inside or external to said integrated circuit or circuit assembly.
  - 18. The apparatus of claim 1, wherein said means for analyzing output responses further comprises means for selectively compacting said N output responses to signatures using a compact operation.
  - 19. The apparatus of claim 1, wherein means for analyzing output responses further comprises means for comparing said signatures with their expected signatures after a predetermined limiting criterion is reached;
    - wherein said means for comparing said signatures with their expected signatures further comprises means for comparing said signatures inside said integrated circuit or circuit assembly, or shifting-out said signatures for comparison in an ATE (automatic test equipment).
  - 20. The apparatus of claim 1, wherein said scan cell is selectively a multiplexed D flip-flop or a level-sensitive scan latch, and further wherein said integrated circuit or circuit assembly under test is a full-scan or partial-scan design.
  - 21. The apparatus of claim 1, wherein said faults further comprise stuck-at faults and delay faults;
    - wherein said stuck-at faults further comprise other stuck-type faults, such as open faults and bridging faults, and wherein said delay faults further comprise other non-stuck-type delay faults, such as transition (gate-delay) faults, multiple-cycle delay faults, and path-delay faults.

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Current Assignee
Syntest Technologies Incorporated
Original Assignee
Syntest Technologies Incorporated
Inventors
Wang, Laung-Terng, Kao, Shih-Chia, Wang, Hsin-Po, Wen, Xiaoqing, Hsu, Po-Ching, Chao, Hao-Jan, Lin, Meng-Chyi
Primary Examiner(s)
BRITT, CYNTHIA H

Application Number

US12/222,931
Publication Number

US 20090132880A1
Time in Patent Office

727 Days
Field of Search

714/724, 714/726, 714/731, 714/732, 714/744, 714/741
US Class Current

714/731
CPC Class Codes

G01R 31/31704   Design for test; Design ver...

G01R 31/318552   Clock circuits details

G01R 31/318594   Timing aspects clock circui...

G06F 30/327   Logic synthesis; Behaviour ...

G06F 30/33   Design verification, e.g. f...

G06F 30/3308   using simulation

G06F 30/3312   Timing analysis

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

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Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

First Claim

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Abstract

19 Citations

21 Claims

Specification

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